Power efficient processor architecture

A method comprising:

• causing a core of a second plurality of cores of a processor to execute an operation, the processor comprising a first plurality of cores, the second plurality of cores, an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores, and a shared cache memory coupled to at least the first plurality of cores, the core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
• causing, based at least in part on a performance requirement, an execution state to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
• analyzing a plurality of interrupts;
• and
• if a majority of the plurality of interrupts are to be handled by the first plurality of cores, waking the core of the first plurality of cores to handle an interrupt and not waking the core of the second plurality of cores.

At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:

• cause a core of a second plurality of cores of a processor to execute an operation, the processor comprising a first plurality of cores, the second plurality of cores, an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores, and a shared cache memory coupled to at least the first plurality of cores, the core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores;
• cause, based at least in part on a performance requirement, an execution state to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation;
• analyze a plurality of interrupts;
• and
• if a majority of the plurality of interrupts are to be handled by the first plurality of cores, wake the core of the first plurality of cores to handle the interrupt and not wake the core of the second plurality of cores.