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US 9,870,046 B2Granted
Distribution of tasks among asymmetric processing elements
AssigneeIntel Corporation
InventorsHerbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
Life of this patent
Estimating the term…
Abstract
Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system
Claims12
A processor comprising:
- a plurality of processing cores, the plurality of processing cores including first and second processing cores, and at least one low-power processing core, wherein at least one of the first and second processing cores and the at least one low-power processing core implement different instruction set architectures (ISAs), and wherein the at least one of the first and second processing cores is to implement a complex instruction set computing (CISC) architecture and is operable at a performance level higher than a performance level of the at least one low-power processing core, the at least one low-power processing core to implement a reduced instruction set computing (RISC) architecture;
- and
- hardware logic coupled to the plurality of processing cores, the hardware logic to help transition tasks from the at least one low-power processing core to at least one of the first and second processing cores to optimize performance and power, wherein the hardware logic is to:
- monitor an activity level of one or more tasks performed on the first processing core, and, independently of an operating system operating on the processor, to:
- transfer the one or more tasks from the first processing core to the at least one low-power processing core when it is determined that the one or more tasks may be run on a lower power or performance core while maintaining an acceptable performance level;
- and
- transfer the one or more tasks from the at least one low-power processing core to the first processing core when the activity level on the at least one low-power processing core exceeds a threshold value;
- wherein instructions to run on the at least one low-power processing core are to be translated from the instruction set of the first processing core to the instruction set of the at least one low-power processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.
5 more elements
A processor comprising:
- a plurality of processing cores including first and second processing cores, and at least one low-power processing core, wherein at least one of the first and second processing cores and the at least one low-power processing core implement different instruction set architectures (ISAs);
- and
- hardware logic coupled to the plurality of processing cores to optimize performance and power by transitioning tasks from the at least one low-power processing core to the first processing core, wherein the hardware logic is to:
- monitor an activity level of one or more tasks performed on the first processing core, and, independently of an operating system operating on the processor, to:
- transfer the one or more tasks from the first processing core to the at least one low-power processing core when it is determined that the one or more tasks may be run on a lower power or performance core while maintaining an acceptable performance level;
- and
- transfer the one or more tasks from the at least one low-power processing core to the first processing core when the activity level on the at least one low-power processing core exceeds a threshold value;
- wherein instructions to run on the at least one low-power processing core are to be translated from the instruction set of the first processing core to the instruction set of the at least one low-power processing core by a software binary translation shell, and wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.
5 more elements
Dependencies are inferred from the claim text.