Method and apparatus for a zero voltage processor sleep state
AssigneeIntel Corporation
InventorsSanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
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Abstract
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Claims21
A system comprising:
- at least one processor comprising a first core and a second core;
- voltage regulation circuitry to regulate an operational voltage of the first core and the second core;
- an interconnect to couple one of the at least one processor to one or more system components;
- and
- a system memory coupled to one of the at least one processor,
- one of the at least one processor comprising:
- the first core to execute sequences of instructions;
- the second core to execute sequences of instructions;
- a shared cache accessible by both the first core and the second core;
- power management logic to cause the first core to be powered down in a first mode while the second core remains in an active state;
- wherein power to the shared cache is to be maintained to enable access by the second core;
- and
- wherein data associated with the first core is to be preserved when the first core is powered down in the first mode, and in a second mode the first core and the second core are to be powered down and the at least one processor is to enter a package sleep state.
A system comprising:
- at least one processor means comprising a first core and a second core;
- voltage regulation means to regulate an operational voltage of the first core and the second core;
- interconnect means to couple one of the at least one processor means to one or more system components;
- and
- system memory means coupled to the at least one processor means,
- one of the at least one processor means comprising:
- the first core to execute sequences of instructions;
- the second core to execute sequences of instructions;
- shared cache means accessible by both the first core and the second core;
- power management means to cause the first core to be powered down in a first mode while the second core remains in an active state;
- wherein power to the shared cache means is to be maintained to enable access by the second core;
- and
- wherein data associated with the first core is to be preserved when the first core is powered down in the first mode, and in a second mode the first core and the second core are to be powered down and the at least one processor means is to enter a package sleep state.
A method comprising:
- regulating a voltage of first and second cores of a processor with a voltage regulation circuit;
- interconnecting the processor to one or more system components;
- and
- coupling a system memory to the processor,
- the processor comprising:
- the first core to execute sequences of instructions;
- the second core to execute sequences of instructions;
- shared cache circuitry accessible by both the first core and the second core;
- power management circuitry to cause the first core to be powered down while the second core remains in an active state;
- wherein power to the shared cache circuitry is to be maintained to enable access by the second core, and when the second core is to be powered down, a size of the shared cache circuitry is reduced;
- and
- wherein data associated with the first core is to be preserved when the first core is powered down.
Dependencies are inferred from the claim text.