Memory device of adaptively calibrating timing margin and integrated circuit including the same

A memory device for an application processor of a portable device, the memory device comprising:

• a memory core comprising a memory cell;
• and
• a controller configured to receive a gray code signal indicating a timing margin corresponding to an operating power level and to control an operation timing of the memory core based on the timing margin,
• wherein the controller comprises a decoder configured to convert the gray code signal to a binary code signal indicating the timing margin.

A portable device comprising:

• an application processor which comprises:
• a power manager configured to determine an operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal,
• a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, and
• a decoder configured to convert the first gray code signal output from the power manager to a first binary code signal indicating the first timing margin, and to output the first binary code signal to the first memory device;
• a power management integrated circuit (PMIC) configured to supply an operating voltage to the application processor;
• a dynamic random access memory (DRAM);
• and
• a flash memory,
• wherein the power manager is configured to provide, to the first memory device, the operating power level.