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US 9,870,012 B2Granted
Digitally phase locked low dropout regulator apparatus and system using ring oscillators
AssigneeIntel Corporation
InventorsArijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
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Abstract
Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
Claims27
An apparatus comprising:
- a first oscillator to generate a first clock signal;
- a second oscillator to generate a second clock signal;
- a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference;
- and
- an output stage comprising a p-type transistor, coupled to a load, to generate a power supply for the load according to the phase difference, wherein a gate terminal of the p-type transistor is to receive the phase difference as a digital pulse,
- wherein the first and second oscillators include equal number of delay stages.
3 more elements
An apparatus comprising:
- a first oscillator to generate a first clock signal;
- a second oscillator to generate a second clock signal;
- and
- an N-bit Johnson Counter to generate N number of phases of the first and second clock signals, the N number of phases to directly or indirectly regulate power supply for one or more loads, where N is an integer, and wherein the N-bit Johnson Counter comprises an embedded output stage which is to provide the regulated power supply.
1 more element
A system comprising:
- a memory;
- a processor, coupled to the memory, the processor including multiple processing cores, each processing core having one or more low dropout regulators (LDOs), wherein the one or more LDOs comprise:
- a first oscillator to generate a first clock signal;
- a second oscillator to generate a second clock signal;
- a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference;
- and
- an output stage comprising a p-type transistor, coupled to a load, to generate a power supply for the load according to the phase difference, wherein a gate terminal of the p-type transistor is to receive the phase difference as a digital pulse;
- and
- a wireless interface to allow the processor to communicate with other devices.
6 more elements
An apparatus comprising:
- a phase detector to detect phase difference between first and second clock signals generated from respective first and second oscillators, wherein the first and second oscillators include equal number of delay stages;
- and
- an output stage, coupled to a load, to generate a power supply for the load according to the phase difference as a digital pulse.
An apparatus comprising:
- an output stage, to be coupled to a load, to generate a power supply for the load according to a phase difference between first and second clock signals generated from respective first and second oscillators, wherein the output stage comprises a voltage level-shifter coupled to a control logic which is to operate at a supply lower than an input power supply, and wherein the input power supply is coupled to p-type transistor of the output stage.
Dependencies are inferred from the claim text.