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US 9,869,718 B1Granted
Scan test architecture and method for scan testing
AssigneeMicrosemi Solutions (U.S.), Inc.
InventorsHanumantharaya H, Yasushi Takenaka
Life of this patent
Estimating the term…
Abstract
A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.
Claims19
A circuit, comprising:
- a memory comprising a memory input and a memory output;
- a bypass path in parallel with the memory, the bypass path comprising a collar flop in communication with the memory input and the memory output, a first net connecting the memory input to an input of the collar flop and a second net connecting the output of the collar flop to logic downstream of the memory;
- and
- a feedback path connecting the memory output to an input of the collar flop, the collar flop configured to capture, from the feedback path, a fault test vector response.
1 more element
A method for testing for a fault in a circuit the method comprising:
- applying a fault test vector to a logic in the circuit to produce a fault test vector response,
- propagating the fault test vector or the fault test vector response, in parallel, through both a memory in the circuit and a bypass path, the memory having a memory input and a memory output, and the bypass path having a first net connecting the memory input to an input of a collar flop and a second net connecting the output of the collar flop to logic downstream of the memory;
- capturing the fault test vector response output by the memory in the collar flop by passing the fault test vector response output by the memory to the collar flop via a feedback path;
- shifting the fault test vector response out of the collar flop;
- and
- comparing the fault test vector response output by the memory and captured in the collar flop to an ideal response to identify a fault.
3 more elements
Dependencies are inferred from the claim text.