US 9,869,708 B2Granted

Integrated circuit protection during high-current ESD testing

AssigneeInternational Business Machines Corporation

InventorsShunhua Chang, James Paul Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra

Life of this patent

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Abstract

A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.

Claims7

Dependent claims

An electro-static discharge (ESD) test system operable to test ESD capabilities of an integrated circuit, the system comprising:

a floating ground connection;
a first plurality of switch devices;
a first plurality of contacts each operably coupled to the floating ground connection via a corresponding one of the first plurality of switch devices;
a second plurality of switch devices;
a plurality of charge storage devices each having a first terminal and a second terminal, the first terminal of each of the plurality of charge storage devices operably coupled to the floating ground connection via a corresponding one of the second plurality of switch devices;
and
a second plurality of contacts each both operably coupled to one of the second plurality of switch devices within the integrated circuit and coupled to the second terminal of a corresponding one of the plurality of charge storage devices.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/882,756Filed 14 Oct 2015 · division
Priority: 13 Apr 2012
Published: US 2016/0033564 A14 Feb 2016
Granted: 16 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G01R 31/002
Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing: where the device…
G01R 31/2851
Testing of electronic circuits, e.g. by signal tracer: testing of integrated circuits [IC]
H02H 9/046
Adapted to a particular application and not provided for elsewhere: responsive to excess voltage appearing at terminals of integrated circuits
H05K 9/0067
Screening of apparatus or components against electric or magnetic fields: devices for protecting against damage from electrostatic discharge

Family

Application13/446,394Parent of this division · filed 13 Apr 2012
US 2016/0033564 A1Pre-grant publication · published 4 Feb 2016
US 9,435,841 B2Parent of this division
US 2013/0271883 A1Published application
US 9,869,708 B2This patent

From the US filing history. Foreign family members aren’t listed.