Printed circuit board and package substrate

A package substrate comprising:

• a lower substrate having at least one electronic device or at least one first chip attached thereto;
• and
• an upper substrate having at least one second chip attached thereto and coupled to the lower substrate,
• wherein the lower substrate comprises:
• an insulating substrate;
• a plurality of pads on a top surface of the insulating substrate;
• a protective layer formed on the insulating substrate and having an opening to expose a top surface of the pads;
• a plurality of bumps provided on the plurality of pads, protruding upward of a surface of the protective layer, and formed on a top surface thereof with a solder ball;
• and
• a plurality of seed layers between the plurality of pads and the plurality of bumps,
• wherein the upper substrate is supported by the plurality of bumps and attached to the lower substrate through the solder ball,
• wherein each of the plurality of bumps comprises:
• a first bump portion filled in the opening of the protective layer and directly connected with a top surface of the one of the pads;
• and
• a second bump portion on the first bump portion and protruding upward of the surface of the protective layer,
• wherein the first bump portion is integrated with the second bump portion,
• wherein an entire lateral side of the second bump portion has a curvature lateral surface,
• wherein a width of the second bump portion is gradually decreased from an upper portion of the second bump portion to a point of inflection and gradually increased from the point of the inflection to a lower portion of the second bump portion,
• wherein a width of the upper portion of the second bump portion is narrower than a width of the lower portion of the second bump portion, and
• wherein the point of the inflection is higher than a central point of the curvature lateral surface of the second bump portion.