Selective segment via plating process and structure
AssigneeMultek Technologies Limited
InventorsKwan Pen, Pui Yin Yu
Life of this patent
Estimating the term…
Abstract
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
Claims16
A circuit board comprising:
- a laminated stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminated stack further comprises an inner plug layer comprising a plurality of plating resist layers, the inner plug layer stacked within an interior of the laminated stack;
- a via formed through the laminated stack, wherein side walls of the via are plated with conductive material except where the via passes through the inner plug layer, thereby forming a via side wall plating discontinuity, wherein the via side walls define a via diameter, and a surface of the via side wall plating facing into the via defines a plated via diameter that is less than the via diameter;
- and
- a plurality of cavities, one cavity for each plating resist layer, each cavity extending transversely from a longitudinal axis of the via at a same layer within the lamented stack as a corresponding plating resist layer, wherein each cavity is defined by cavity side walls that are recessed from the via side walls and by top and bottom surfaces corresponding to layers of the laminated stack adjacently laminated to both sides of the corresponding plating resist layer, wherein the cavity side wall comprises plating resist.
A circuit board comprising:
- a laminated stack comprising a plurality of non-conducting layers and a plurality of conductive layers, wherein the laminated stack further comprises an inner plug layer comprising a plurality of plating resist layers, the inner plug layer, stacked within an interior of the laminated stack;
- a via formed through the laminated stack, wherein side walls of the via are plated with conductive material except where the via passes through the inner plug layer, wherein the via side walls define a via diameter, and a surface of the via side wall plating facing into the via defines a plated via diameter that is less than the via diameter;
- and
- a plurality of cavities, one cavity for each plating resist layer, each cavity extending transversely from a longitudinal axis of the via at a same layer within the lamented stack as a corresponding plating resist layer, wherein each cavity forms a via side wall plating discontinuity, further wherein each cavity is defined by cavity side walls that are recessed from the via side walls and by top and bottom surfaces corresponding to layers of the laminated stack adjacently laminated to both sides of the corresponding plating resist layer, wherein the cavity side wall comprises plating resist, further wherein the via wall plating forms electrical interconnections with conductive layers intersecting the via, and the via wall plating discontinuity electrically isolates a first segment of electrically interconnected conductive layers from a second segment of electrically interconnected conductive layers.
Dependencies are inferred from the claim text.