System and method for signal read-out using source follower feedback

An amplifier circuit comprising:

• a pair of subcircuits comprising a first subcircuit and a second subcircuit, each comprising:
• a buffer amplifier;
• and
• a feedback circuit comprising a feedback capacitor, wherein
• the first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals, the pair of output signals comprises a first output signal and a second output signal, and the amplifier circuit is configured for
• receiving a positive differential input signal at the first subcircuit,
• receiving a negative differential input signal at the second subcircuit,
• transmitting the first output signal to the feedback circuit of the first subcircuit,
• transmitting the second output signal to the feedback circuit of the second subcircuit,
• adjusting, in accordance with a target voltage transfer ratio, a capacitance of the feedback circuit of each of the first subcircuit and the second subcircuit,
• selecting, in accordance with the target voltage transfer ratio, the first output signal from a pair of output signals comprising an output of the first subcircuit and an output of the second subcircuit, and
• selecting, in accordance with the target voltage transfer ratio, the second output signal from the pair of output signals, wherein the second output signal is distinct from the first output signal.

An amplifier circuit comprising:

• a pair of subcircuits comprising a first subcircuit and a second subcircuit, each comprising:
• a buffer amplifier;
• and
• a feedback circuit comprising a feedback capacitor, the first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals, the pair of output signals comprises a first output signal and a second output signal, and the amplifier circuit is configured for
• receiving a positive differential input signal at the first subcircuit,
• receiving a negative differential input signal at the second subcircuit,
• transmitting the first output signal to the feedback circuit of the first subcircuit, and
• transmitting the second output signal to the feedback circuit of the second subcircuit;
• a current bias circuit coupled in series with the buffer amplifier, the current bias circuit comprising a current bias transistor comprising a gate coupled to an output of the feedback circuit;
• a subcircuit input node coupled to a gate of the buffer amplifier;
• a subcircuit output node;
• and
• a feedback node coupled to an input of the feedback circuit, wherein
• a positive input terminal of the amplifier circuit is coupled to the subcircuit input node of the first subcircuit,
• a negative input terminal of the amplifier circuit is coupled to the subcircuit input node of the second subcircuit,
• a first output terminal is coupled to the subcircuit output node of the first subcircuit,
• a second output terminal is coupled to the subcircuit output node of the second subcircuit, and
• a configurable voltage transfer ratio of each of the pair of subcircuits varies in accordance with an amplitude of a current variation through the current bias transistor.

An amplifier system, comprising:

• a pair of subcircuits, each comprising:
• a buffer amplifier;
• a feedback circuit, comprising at least one feedback capacitor;
• and
• a current bias circuit coupled in series with the buffer amplifier, the current bias circuit comprising
• a current bias transistor comprising a gate coupled to an output of the feedback circuit,
• a current source transistor coupled in series with the buffer amplifier, the current source transistor comprising a gate coupled to an input of the current bias circuit, and
• a plurality of cascode transistors coupled to the gate of the current source transistor and coupled in series with the current bias transistor;
• an input node coupled to a gate of the buffer amplifier;
• an output node;
• a feedback node coupled to an input of the feedback circuit;
• a positive differential input terminal coupled to the input node of a first subcircuit of the pair of subcircuits;
• a negative differential input terminal coupled to the input node of a second subcircuit of the pair of subcircuits;
• a pair of output terminals comprising a first output terminal and a second output terminal, wherein
• the feedback node of each of the pair of subcircuits is coupled to a different one of the pair of output terminals,
• the first output terminal is coupled to the output node of the first subcircuit, and
• the second output terminal is coupled to the output node of the second subcircuit;
• and
• a voltage bias circuit configured to provide a plurality of bias voltages comprising a first bias voltage, a second bias voltage, and a third bias voltage, wherein
• the first bias voltage is coupled to the positive differential input terminal and to the negative differential input terminal, and
• the plurality of cascode transistors comprises
• a p-channel cascode transistor coupled in series with the gate of the current source transistor, the p-channel cascode transistor comprising a gate coupled to the second bias voltage, and
• a n-channel cascode transistor coupled in series with the p-channel cascode transistor and with the gate of the current source transistor, the n-channel cascode transistor comprising a gate coupled to the third bias voltage.