Apparatus and method for single antenna interference cancellation (SAIC) enhancement

A method of combining channels of a de-rotated signal by an interference cancelation (IC) processor, comprising:

• generating an effective channel hres,i and an estimated filter pi by each of a plurality of mono interference cancellation (MIC) filter estimation processors, wherein each of the plurality of MIC filter estimation processors includes a different equalizer offset k0 and includes an input connected to a first input of the IC processor for receiving a de-rotated signal;
• filtering, by a plurality of filters, the generating effective channels hres,i of each of the plurality of MIC filter estimation processors;
• multiplying, by a plurality of multipliers, each of the filtered effective channels hres,i of the plurality of filters by one of a plurality of weights;
• and
• generating, by a branch combiner, a combined residual channel Hres and a projected output y of the de-rotated signal.

A method of manufacturing a semiconductor device, comprising:

• forming the semiconductor device as part of a wafer or package that includes a plurality of mono interference cancellation (MIC) filter estimation processors, wherein each of the plurality of MIC filter estimation processors includes a different equalizer offset k0 and includes an input connected to a first input of the IC processor for receiving a de-rotated signal, and a first output that provides an effective channel hres,i and an estimated filter pi;
• a plurality of filters, wherein each of the plurality of filters includes an input connected to the output of one of the plurality of MIC filter estimation processors, and an output;
• a plurality of multipliers, wherein each of the plurality of multipliers includes a first input connected to the output of one of the plurality of filters, a second input for receiving a weight, and an output;
• and
• a branch combiner including a plurality of inputs connected to the outputs of the plurality of multipliers, a first output connected to a first output of the IC processor for providing a combined residual channel Hres, and a second output connected to a second output of the IC processor for providing a projected output y of the de-rotated signal;
• and
• testing the semiconductor device, wherein testing of the semiconductor device is performed using at least one electrical to optical converter, at least one optical splitter that splits an optical signal into at least two optical signals, and at least one optical to electrical converter.

A method of constructing an integrated circuit, comprising:

• generating a mask layout for a set of features for a layer of the integrated circuit, the mask layout having standard cell library macros for:
• a plurality of mono interference cancellation (MIC) filter estimation processors, wherein each of the plurality of MIC filter estimation processors includes a different equalizer offset k0 and includes an input connected to a first input of the IC processor for receiving a de-rotated signal, and a first output that provides an effective channel hres,i and an estimated filter pi;
• a plurality of filters, wherein each of the plurality of filters includes an input connected to the output of one of the plurality of MIC filter estimation processors, and an output;
• a plurality of multipliers, wherein each of the plurality of multipliers includes a first input connected to the output of one of the plurality of filters, a second input for receiving a weight, and an output;
• and
• a branch combiner including a plurality of inputs connected to the outputs of the plurality of multipliers, a first output connected to a first output of the IC processor for providing a combined residual channel Hres, and a second output connected to a second output of the IC processor for providing a projected output y of the de-rotated signal;
• disregarding relative positions of the macros for layout design rule compliance during generation of the mask layout;
• monitoring the relative positions of the macros for layout design rule compliance after disregarding the relative positions;
• upon detection of layout design rule noncompliance of the macros, generating an adapted mask layout by adapting the noncompliance macros for layout design rule compliance;
• generating a mask according to the adapted layout with the set of features for the layer of the integrated circuit;
• and
• manufacturing the integrated circuit layer according to the mask.