US 9,866,238 B1Granted

Incremental analog to digital converter with efficient residue conversion

AssigneeSilicon Laboratories Inc.

InventorsAxel Thomsen, Xiaodong Wang

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Abstract

An incremental analog to digital converter for digitizing an analog voltage including an Mth order delta sigma modulator, an Mth order digital decimation filter, a controller, and a digital combiner. The controller operates the modulator to convert the analog voltage into multiple digital samples, and operates the digital decimation filter to convert the digital samples into a preliminary digital output value. The controller further operates the delta sigma modulator during a residue phase for M clock cycles in which the modulator provides a digital residue value. The digital combiner combines the preliminary digital output value with the digital residue value to provide an initial digital output value. For an Mth order system, only M additional cycles are needed to extract the residual value to increase the resolution of the digital output by an amount based on the resolution of a modulator quantizer.

Claims20

Dependent claims

An incremental analog to digital converter for digitizing an analog voltage, comprising:

a delta sigma modulator having an input for receiving the analog voltage and having an output, wherein said delta sigma modulator comprises M analog integrators in which M is at least one;
a digital decimation filter comprising M digital integrators, said digital decimation filter having an input selectively coupled to said output of said delta sigma modulator and having an output;
a controller that operates said delta sigma modulator and said digital decimation filter for at least one conversion cycle, wherein said controller:
resets said delta sigma modulator and said digital decimation filter during a reset stage;
operates said delta sigma modulator and said digital decimation filter for a plurality of clock cycles during a delta sigma phase wherein said delta sigma modulator converts the analog voltage into a corresponding plurality of digital samples, and wherein said digital decimation filter converts said plurality of digital samples into a preliminary digital output value;
and
operates said delta sigma modulator during a residue phase for M clock cycles wherein said delta sigma modulator provides a digital residue value at said output of said delta sigma modulator;
and
a digital combiner that combines said preliminary digital output value with said digital residue value to provide an initial digital output value.

6 more elements

A method of digitizing an analog voltage, comprising:

resetting integrators of an Mth order delta sigma modulator and an Mth order digital decimation filter during a reset phase, wherein M is at least one;
operating the delta sigma modulator for a plurality of clock cycles during a delta sigma phase for converting the analog voltage into a corresponding plurality of digital samples at an output of the delta sigma modulator;
operating the digital decimation filter for the plurality of clock cycles during the delta sigma phase for converting the plurality of digital samples into a preliminary digital output value;
operating the delta sigma modulator during a residue phase for an additional M clock cycles for providing a digital residue value at the output of the delta sigma modulator;
and
digitally combining the preliminary digital output value with the digital residue value during an output phase to provide an initial digital output value.

3 more elements

Dependencies are inferred from the claim text.