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US 9,866,237 B1Granted
Low power switched capacitor integrator, analog-to-digital converter and switched capacitor amplifier
AssigneeTexas Instruments Incorporated
InventorsRajavelu Thinakaran, Sumit Dubey
Life of this patent
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Abstract
Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.
Claims20
An integrator circuit, comprising:
- an amplifier, including a first amplifier input, a second amplifier input connected to a constant voltage node, and an amplifier output to provide an integrator output signal;
- a feedback capacitor coupled between the first amplifier input and the amplifier output;
- a sampling capacitor, including a first terminal, and a second terminal;
- a loading capacitor, including a first terminal, and a second terminal;
- a switching circuit coupled with the amplifier, an integrator input node, a reference voltage node, and the constant voltage node;
- and
- a controller, including signal outputs to provide switching control signals in each of a series of successive sample and hold cycles to cause the switching circuit to:
- connect an integrator input signal from the integrator input node to the sampling capacitor during a first non-zero time period in a sample portion of each sample and hold cycle,
- couple the sampling capacitor between the reference voltage node and the first amplifier input during a second non-zero time period following the first non-zero time period in a first hold portion of each sample and hold cycle, and
- couple the sampling capacitor and the loading capacitor to the first amplifier input to reduce a bandwidth of the integrator circuit and reduce power consumption by the integrator circuit during a third non-zero time period following the second non-zero time period in a second hold portion of each sample and hold cycle.
7 more elements
An integrator circuit, comprising:
- an amplifier, including a first amplifier input, a second amplifier input connected to a constant voltage node, and an amplifier output to provide an amplifier output signal;
- a feedback capacitor coupled between the first amplifier input and an integrator circuit output to provide an integrator circuit output signal;
- a sampling capacitor, including a first terminal, and a second terminal;
- a loading capacitor, including a first terminal, and a second terminal;
- an output capacitor, including a first terminal coupled with the amplifier output, and a second terminal connected to the integrator circuit output;
- a switching circuit coupled with the amplifier, an integrator input node, a reference voltage node, and the constant voltage node;
- and
- a controller, including signal outputs to provide switching control signals in each of a series of successive sample and hold cycles to cause the switching circuit to:
- connect an integrator input signal from the integrator input node to the sampling capacitor during a first non-zero time period in a sample portion of each of a series of successive sample and hold cycles,
- couple the sampling capacitor between the reference voltage node and the first amplifier input during a second non-zero time period following the first non-zero time period in a first hold portion of each sample and hold cycle, and
- couple the sampling capacitor with the first amplifier input and couple the loading capacitor to the amplifier output to reduce a bandwidth of the integrator circuit and reduce power consumption by the integrator circuit during a third non-zero time period following the second non-zero time period in a second hold portion of each given sample and hold cycle.
8 more elements
A switched capacitor amplifier circuit, comprising:
- an amplifier, including a first amplifier input, a second amplifier input connected to a constant voltage node, and an amplifier output to provide an output signal;
- a feedback capacitor connected between the first amplifier input and the amplifier output;
- a sampling capacitor, including a first terminal, and a second terminal connected to the first amplifier input;
- a loading capacitor, including a first terminal, and a second terminal;
- a switching circuit coupled with the amplifier, a signal input node, a reference voltage node, and the constant voltage node;
- and
- a controller, including signal outputs to provide switching control signals in each of a series of successive cycles to cause the switching circuit to:
- connect the signal input node to the first terminal of the sampling capacitor during a first non-zero time period in a sample portion of each cycle, and connect the first amplifier input to the amplifier output during the first non-zero time period of each cycle,
- disconnect the signal input node from the first terminal of the sampling capacitor during a second non-zero time period following the first non-zero time period in a first hold portion of each cycle, and connect the sampling capacitor between the reference voltage node and the first amplifier input during the second non-zero time period, and
- connect the sampling capacitor and the loading capacitor to the first amplifier input to reduce a bandwidth of the amplifier circuit and reduce power consumption by the amplifier circuit during a third non-zero time period following the second non-zero time period in a second hold portion of each cycle.
7 more elements
Dependencies are inferred from the claim text.