Clock recovery circuit, related clock and data recovery circuit, receiver, integrated circuit and method

A device, comprising:

• an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal;
• oscillator control circuitry, which, in operation:
• determines a phase error between a reference signal and the clock signal;
• detects cycle-slippage based on whether the phase error is within a threshold phase-error range;
• and
• generates the control signal based on the determined phase error and on whether cycle-slippage has been detected;
• and
• a frequency tracking control loop, which, in operation:
• determines a frequency difference between said clock signal and said reference signal;
• and
• modifies said control signal as a function of said frequency difference, wherein said frequency tracking control loop has a response time greater than a response time of a phase tracking loop of the oscillator control circuitry.

A system, comprising:

• a clock recovery circuit, including:
• an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal;
• a phase-tracking loop, which, in operation:
• determines a phase error between a data signal and the clock signal;
• and
• generates the control signal based on the determined phase error;
• and
• cycle-slippage detection circuitry, which, in operation:
• detects cycle-slippage based on whether the phase error is within a threshold phase-error range;
• and
• modifies the control signal in response to detection of cycle slippage;
• and
• data-recovery circuitry, which, in operation recovers data transmitted via said data signal as a function of said clock signal and said data signal, wherein said cycle-slippage detection circuitry, in operation:
• generates at least one positive charge pulse when said phase error approaches or reaches +π;
• and
• generates at least one negative charge pulse when said phase error approaches or reaches −π.

A method, comprising:

• generating a clock signal having a frequency based on a control signal;
• determining a phase error between a reference signal and the clock signal;
• detecting cycle-slippage based on whether the phase error is within a threshold phase-error range;
• and
• generating the control signal based on the determined phase error and on whether cycle-slippage has been detected, wherein the method includes:
• generating at least one positive charge pulse when said phase error approaches or reaches +π;
• and
• generating at least one negative charge pulse n said phase error approaches or reaches −π.

A system, comprising:

• means for generating a clock signal;
• and
• means for controlling the means for generating the clock signal based on:
• a phase error between a data signal and the clock signal;
• and
• detection of cycle-slippage, wherein cycle-slippage is detected based on whether the phase error between said data signal and said clock signal reaches or approaches +π or −π, wherein the means for controlling includes means for generating:
• at least one positive charge pulse when said phase error approaches or reaches +π;
• and
• at least one negative charge pulse when said phase error approaches or reaches −π.

A system, comprising:

• a clock recovery circuit, including:
• an oscillator, which, in operation, generates a clock signal having a frequency based on a control signal;
• a phase-tracking loop, which, in operation:
• determines a phase error between a data signal and the clock signal;
• and
• generates the control signal based on the determined phase error;
• and
• cycle-slippage detection circuitry, which, in operation:
• detects cycle-slippage based on whether the phase error is within a threshold phase-error range;
• and
• modifies the control signal in response to detection of cycle slippage;
• and
• data-recovery circuitry, which, in operation recovers data transmitted via said data signal as a function of said clock signal and said data signal, wherein the clock recovery circuit includes a frequency tracking control loop, which, in operation:
• determines a frequency difference between said clock signal and said data signal;
• and
• modifies said control signal as a function of said frequency difference, wherein said frequency tracking control loop has a response time greater than a response time of the phase tracking loop.

A method, comprising:

• generating a clock signal having a frequency based on a control signal;
• determining a phase error between a reference signal and the clock signal;
• detecting cycle-slippage based on whether the phase error is within a threshold phase-error range;
• and
• generating the control signal based on the determined phase error and on whether cycle-slippage has been detected, wherein the method includes:
• determining a frequency difference between said clock signal and said reference signal;
• and
• modifying said control signal as a function of said frequency difference, wherein a frequency tracking control loop which determines the frequency difference has a response time greater than a response time of a phase tracking loop which determines the phase difference.