US 9,866,220 B2 · Timing device

Abstract

A timing method and a timing device are disclosed. A Gray code count output may be obtained by performing a Gray code count on a basic clock. Then m number of sub-clocks may be obtained by separately performing a phase shift on a least significant bit output of the Gray code count output, where a phase difference φ between each of the m number of sub-clocks and the least significant bit output may satisfy: φ=n×α and φ≠90°, 180° may be divisible by α with no remainder, and n may be an integer greater than 0 and less than 180°/α. If 90° is divisible by α with no remainder, m=180/α−2; and if 90° is divisible by α with a remainder, m=180/α−1. When a predetermined event occurs, a timing result of the predetermined event may be obtained according to the Gray code count output value, outputs of the m number of sub-clocks, a period of the basic clock, and the α.

Claims12

Dependent claims

A timing method, comprising:

obtaining a Gray code count output by performing a Gray code count on a basic clock;
obtaining m number of sub-clocks by separately performing a phase shift on a least significant bit output of the Gray code count output, wherein a phase difference φ between each of the m number of sub-clocks and the least significant bit output satisfies:
φ=n×α and φ≠90°, wherein, 180° is divisible by α with no remainder, and n is an integer greater than 0 and less than 180°/α;
when 90° is divisible by α with no remainder, m=180/α−2,
when 90° is divisible by α with a remainder, m=180/α−1;
and
obtaining a timing result of a predetermined event according to the Gray code count output value, outputs of the m number of sub-clocks, a period of the basic clock, and the α when the predetermined event occurs.

4 more elements

A timing device, comprising:

a count module configured to obtain a Gray code count output by performing a Gray code count on a basic clock;
m number of sub-clock modules respectively configured to obtain a sub-clock by performing a phase shift on a least significant bit output of the Gray code count output, wherein a phase difference φ between each of the m number of sub-clocks and the least significant bit output satisfies:
φ=n×α and φ≠90°, wherein 180° is divisible by α with no remainder, and n is an integer greater than 0 and less than 180°/α;
when 90° is divisible by a with no remainder, m=180/α−2,
when 90° is divisible by a with no remainder, m=180/α−1;
a latch module configured to latch the Gray code count output and outputs of m number of sub-clocks obtained by the m number of sub-clock modules when a predetermined event occurs;
and
a timing module configured to obtain a timing result of the predetermined event according to the Gray code count output value, outputs of the m number of sub-clocks, a period of the basic clock, and the α.

5 more elements

Dependencies are inferred from the claim text.

Timing device

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Timing device

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Abstract

Claims12