Boolean logic in a state machine lattice
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown, Paul Glendenning, Irene J. Xu
Life of this patent
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Abstract
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
Claims24
A system, comprising:
- a state machine engine comprising a state machine lattice, wherein the state machine lattice comprises:
- a plurality of blocks each comprising a plurality of rows, each of the rows comprising a plurality of programmable elements, wherein a particular one of the programmable elements is configured to output a signal based on a detection of a condition;
- and
- at least one of the rows of a particular one of the blocks further comprising a Boolean logic cell configured to be selectively coupleable to any of the programmable elements in any of the plurality of rows of the particular one of the blocks, wherein the Boolean logic cell is configured to output a result of a logical function.
A method of performing a logic operation at a Boolean logic cell in a state machine lattice, the method comprising:
- receiving a data stream at a bus interface from a memory;
- processing the data stream in the state machine lattice to detect a plurality of conditions;
- performing a logic function on the detected conditions in a programmable Boolean logic cell in the state machine lattice;
- and
- outputting a result of the logic function via the bus interface to a processor.
A system, comprising:
- a state machine lattice comprising:
- programmable elements;
- and
- a Boolean logic cell, wherein the Boolean logic cell is configured to be selectively coupled to the programmable elements, wherein the Boolean logic cell is configured to receive inputs from outputs of the programmable elements selectively coupled thereto and to be programmable to perform a selected logic function of a plurality of possible logic functions on the inputs;
- and
- an interface bus configured to receive programming instructions to initially configure the programmable elements and the Boolean logic cell, wherein the interface bus is configured to transmit at least one search result from the state machine lattice to a processor.
Dependencies are inferred from the claim text.