Radio frequency switch with improved switching time

A semiconductor substrate having an RF switch circuit fabricated thereon, wherein the RF switch circuit comprises:

• an RF domain section having a plurality of RF switching elements;
• a DC domain section having circuitry configured for controlling the RF switching elements in response to one or more control signals;
• wherein the DC domain section comprises an oscillator for generating a clock signal, the oscillator includes a biasing stage having a variable resistive load which is configurable for varying the frequency of the clock signal, and
• an asynchronous detection section configured to generate a state change detection signal without requiring input of an external system clock signal for determining when to vary the variable resistive load, the detection section being configured to generate the state change detection signal from the one or more control signals and one or more delayed control signals having an associated delay offset time period, wherein the detection section generates the state change detection signal for a time period corresponding to the delay offset time period when any one of the one or more control signals is transitioning between logic states.

A method of fabricating an RF switch circuit, the method comprising:

• providing an RF domain section having a plurality of RF switching elements on a semiconductor substrate;
• providing a DC domain section on the semiconductor substrate having circuitry configured for controlling the RF switching elements in response to one or more control signals;
• wherein the DC domain section comprises an oscillator for generating a clock signal, the oscillator includes a biasing stage having a variable resistive load which is configurable for varying the frequency of the clock signal, and
• providing an asynchronous detection section configured to generate a state change detection signal without requiring input of an external system clock signal for determining when to vary the variable resistive load, the detection section being configured to generate the state change detection signal from the one or more control signals and one or more delayed control signals having an associated delay offset time period, wherein the detection section generates the state change detection signal for a time period corresponding to the delay offset time period when any one of the one or more control signals is transitioning between logic states.

A radio frequency (RF) switch comprising:

• an RF domain section having a plurality of RF switching elements;
• a DC domain section having circuitry configured for controlling the RF switching elements in response to one or more control signals;
• wherein the DC domain section comprises an oscillator for generating a clock signal, the oscillator includes a biasing stage having a variable resistive load which is configurable for varying the frequency of the clock signal, and
• an asynchronous detection section configured to generate a state change detection signal without requiring input of an external system clock signal for determining when to vary the variable resistive load when at least one signal asynchronously derived from the one or more control signals is transitioning between logic states, the detection section being configured to generate the state change detection signal from the one or more control signals and one or more delayed control signals having an associated delay offset time period, wherein the detection section generates the state change detection signal for a time period corresponding to the delay offset time period when any one of the one or more control signals is transitioning between logic states.

A radio frequency (RF) switch comprising:

• an RF domain section having a plurality of RF switching elements;
• a DC domain section having circuitry configured for controlling the RF switching elements in response to one or more control signals, the DC domain section comprising an oscillator for generating a clock signal, the oscillator including a biasing stage having a variable resistive load that is configurable for varying the frequency of the clock signal;
• a bypassable resistive load provided between the RF domain section and the DC domain section, the bypassable resistive load comprising an equivalent resistance provided between an output node of a filter and a terminal of respective RF switching elements of the plurality of RF switching elements;
• a bypass circuit configured for selectively bypassing at least a portion of the bypassable resistive load;
• and
• an asynchronous detection section configured to generate a state change detection signal without requiring input of an external system clock signal for determining when to vary the variable resistive load, the detection section being configured to generate the state change detection signal from the one or more control signals and one or more delayed control signals having an associated delay offset time period, wherein the detection section generates the state change detection signal for a time period corresponding to the delay offset time period when any one of the one or more control signals is transitioning between logic states.

A radio frequency (RF) switch comprising:

• an RF domain section having a plurality of RF switching elements;
• a DC domain section having circuitry configured for controlling the RF switching elements in response to one or more control signals;
• a resistive load provided between the RF domain section and the DC domain section;
• a bypass circuit configured for selectively bypassing at least a portion of the resistive load;
• and
• an asynchronous detection stage being operable without requiring input of an external system clock signal and comprising one or more logic gates configured to implement an exclusive OR gate function.