US 9,866,204 B1Granted

Latch circuit with isolated input and/or output

AssigneeLockheed Martin Corporation

InventorsToshi Omori, Brandon R. Davis, Lloyd F. Linder, Victoria T. Pereira

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Abstract

A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

Claims17

Dependent claims

A latch circuit comprising:

a pair of input transistors that receive a differential input signal, wherein a first input transistor receives a positive input signal and a second input transistor receives a negative input signal;
a plurality of steering transistors, each transistor in the plurality of steering transistors configured to receive one component of a differential clock signal;
a first bypass input current path coupled to the first input transistor, wherein the first bypass input current path is electrically isolated from a positive output node and a negative output node;
and
a second bypass input current path coupled to the second input transistor, wherein the second bypass input current path is electrically isolated from the positive output node and the negative output node;
wherein on a condition that the latch circuit is in a latched state, the differential clock signal is operative to selectively bias one or more of the plurality of steering transistors such that an input current based on the differential input signal is steered to one of the first bypass input current path or the second bypass input current path.

3 more elements

A method of preventing input feed-through in a latch circuit, the method comprising the steps of:

defining a first bypass input current path, which is isolated from output nodes of the latch circuit, the first bypass input current path associated with a first input transistor of the latch circuit;
defining a second bypass input current path, which is isolated from the output nodes of the latch circuit, the second bypass input current path associated with a second input transistor of the latch circuit;
connecting a first current source to one or more input current paths;
connecting a second current source to one or more output current paths;
selectively applying a differential clock signal to a plurality of steering transistors, the differential clock signal operable to place the latch circuit in a first state in which the latch circuit is latched and a second state in which the latch circuit is unlatched;
selectively steering an input current associated with one of the first input transistor and the second input transistor through at least one of the first bypass input current path and the second bypass input current path, and selectively steering an output current through at least one of a first output node and a second output node on a condition that the latch circuit is placed in the first state in which the latch circuit is latched.

3 more elements

Dependencies are inferred from the claim text.