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US 9,866,018 B2Granted
System and method for transistor voltage control
AssigneeDell Products L.P.
InventorsWickman (Feng-Yu) Wu, Vincent Chia Hung Chen
Life of this patent
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Abstract
Systems and methods are drawn to controlling transistor gate voltages in load-switcher circuitry. A buffer may be applied to a load-switcher transistor to leverage the Miller effect. A slow gate charge circuit may be coupled to the gate of the transistor to control application of voltage to the gate and capacitances associated therewith. The buffer and slow gate charge circuit may be used in conjunction to control characteristics of the voltage applied to the gate of the transistor.
Claims19
An apparatus comprising:
- a voltage regulator;
- control circuitry coupled to control the voltage regulator;
- and
- load-switcher circuitry coupled to receive power output from the voltage regulator and coupled to receive control signals from the control circuitry, the load switcher circuitry including a transistor and a buffer coupled between a gate and a drain of the transistor.
1 more element
A method comprising:
- in load-switcher circuitry configured to drive a load and including a load-driving transistor, coupling a buffer between a transistor output driving the load and a gate of the transistor;
- and
- coupling a slow gate charge circuit between the gate and a control voltage.
Load-switcher circuitry comprising:
- a load-driving transistor;
- and
- a slow gate charge circuit coupling a control voltage to a gate of the load-driving transistor, wherein a parasitic capacitance associated with the gate charges and discharges via the slow gate charge circuit;
- and
- a buffer coupled between a transistor output of the load-driving transistor and the gate.
2 more elements
Dependencies are inferred from the claim text.