Semiconductor memory devices for use in electrically alterable read only memory (ROM) and semiconductor thin film devices (spintrons and spin-orbitrons)
OwnerEugeniy Troyaninventor
Life of this patent
Estimating the term…
Abstract
An electrically alterable thin film memory device or non-volatile trigger which can be switched from a high resistance state to a low resistance state. The device increases the concentration of electrically active impurities at correspondent electrodes to which respect impurities would electro migrate during a large number of set-reset cycles. The device comprises a layered structure with memory layers formed on an interface of two regions as the result of the mutual mixing and migration of their constituents. One region contains an electrically active donor impurity. A thin layer of dielectric is placed in the other region. Each of the memory layers includes an interface of chalcogenide films.
Claims15
An electrically alterable memory device or non-volatile trigger, comprising:
- a plurality of electrodes in electrical communication with a stacked chalcogenide material, said stacked chalcogenide material including a lower memory cell and an upper memory cell and a central area located between said lower memory cell and said upper memory cell;
- wherein each of said upper and lower memory cells includes a chalcogenide alloy and an interface between said central area and said chalcogenide alloy and represents a layered structure with a memory layer that is formed on the respective interface between said central area and each of said chalcogenide alloys;
- wherein each said chalcogenide alloy includes an intermediate thin film layer of a dielectric interposed therebetween, said thin film layer of said dielectric used as a source of negatively charged impurities in said chalcogenide alloy;
- wherein said central area comprises a chalcogenide-metal ion material including an ion source layer and lower and upper Tellurium layers having varying concentration profiles of additives composed of positively charged impurities;
- wherein each of said memory layers is formed on said interface as a result of mutual diffusion and mixing of constituents;
- wherein said plurality of electrodes include a first electrode, a second electrode, and two offset electrodes, said first electrode positioned beneath and electrically coupled to said chalcogenide alloy of said lower memory cell, said second electrode positioned above and electrically coupled to said chalcogenide alloy of said upper memory cell, and said two offset electrodes interposed between said first and said second electrodes and electrically coupled to said ion source layer of said central area.
Dependencies are inferred from the claim text.