Electronic device and method for fabricating the same
AssigneeSK hynix Inc.
InventorJu-Bong Park
Life of this patent
Estimating the term…
Abstract
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.
Claims19
An electronic device comprising a semiconductor memory,
- wherein the semiconductor memory comprises:
- a substrate;
- a variable resistance element formed over the substrate;
- a top electrode formed over the variable resistance element;
- a barrier layer formed over the top electrode and including a groove that is located in an upper portion of the barrier layer and is above both the top electrode and the variable resistance element underneath the top electrode;
- an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer;
- and
- a metal wiring including a portion formed in the groove of the barrier layer.
An electronic device comprising a semiconductor memory including an array of unit cells,
- wherein each unit cell comprises:
- a substrate;
- a bottom electrode contact formed over the substrate through a first interlayer dielectric layer;
- a variable resistance element formed over the first interlayer dielectric layer through a second interlayer dielectric layer and including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer interposed between the first and second magnetic layers, the variable resistance element being electrically coupled to the substrate through the bottom electrode contact and exhibiting different resistance states for storing data based on magnetization directions of the first magnetic layer and the second magnetic layer;
- a top electrode contact formed over the variable resistance element in the second interlayer dielectric layer;
- a metal wiring formed over the top electrode contact to be electrically coupled to the variable resistance element through the top electrode contact;
- and
- a barrier layer formed over the top electrode contact and surrounding at least a portion of the metal wiring, and
- wherein the barrier layer includes a groove that is located in an upper portion of the barrier layer and is above both the top electrode contact and the variable resistance element underneath the top electrode contact.
An electronic device comprising a semiconductor memory including an array of unit cells,
- wherein each unit cell comprises:
- a substrate;
- a bottom electrode contact formed over the substrate through a first interlayer dielectric layer;
- a variable resistance element formed over the first interlayer dielectric layer through a second interlayer dielectric layer and including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer interposed between the first and second magnetic layers, the variable resistance element being electrically coupled to the substrate through the bottom electrode contact and exhibiting different resistance states for storing data based on magnetization directions of the first magnetic layer and the second magnetic layer;
- a top electrode contact formed over the variable resistance element in the second interlayer dielectric layer;
- a metal wiring formed over the top electrode contact to be electrically coupled to the variable resistance element through the top electrode contact;
- and
- a barrier layer formed over the top electrode contact and surrounding at least a portion of the metal wiring, and
- wherein the barrier layer is formed to surround the entire metal wiring, and
- wherein the barrier layer has a variable thickness such that the top critical dimension of the metal wiring including the barrier layer is equal to the bottom critical dimension of the metal wiring including the barrier layer.
Dependencies are inferred from the claim text.