Electronic device
AssigneeSK hynix Inc.
InventorsJeong-Myeong Kim, June-Seo Kim, Jong-Koo Lim, Jung-Hwan Moon, Sung-Joon Yoon
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Abstract
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a pinned layer having a pinned magnetization direction; a free layer having a changeable magnetization direction; a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide; and a carbon-based compound patch positioned at one or more of between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, and in the tunnel barrier layer.
Claims19
An electronic device comprising a semiconductor memory,
- wherein the semiconductor memory comprises:
- a pinned layer having a pinned magnetization direction;
- a free layer having a changeable magnetization direction;
- a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide;
- and
- a carbon-based compound patch positioned between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, or in the tunnel barrier layer, and
- wherein the carbon-based compound patch comprises a graphene, a graphite oxide or a fullerene.
An electronic device comprising a semiconductor memory,
- wherein the semiconductor memory comprises:
- a pinned layer having a pinned magnetization direction;
- a free layer having a changeable magnetization direction;
- a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide;
- and
- a carbon-based compound patch positioned between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, or in the tunnel barrier layer, and wherein the tunnel barrier layer comprises ZnO, and the carbon-based compound patch comprises a graphene.
An electronic device comprising a semiconductor memory,
- wherein the semiconductor memory comprises:
- a first magnetic layer;
- a second magnetic layer;
- and
- a material layer that is interposed between the first and second magnetic layers, and that includes a graphene, a graphite oxide or a fullerene to effectuate a coupling of metal-oxygen-carbon.
An electronic device comprising a semiconductor memory of a plurality of memory cells, each memory cell including a resistance variable element that includes:
- a pinned layer having a pinned magnetization direction;
- a free layer having a changeable magnetization direction;
- a tunnel barrier layer interposed between the pinned layer and the free layer;
- and
- carbon-based compound patches distributed in the tunnel barrier layer, and
- wherein the carbon-based compound patch comprises a graphene, a graphite oxide or a fullerene.
Dependencies are inferred from the claim text.