Fin field effect transistor (FinFET) having air gap and method of fabricating the same

A method of fabricating a vertical fin field effect transistor (V-FinFET), comprising:

• forming a fin structure having a sidewall on a substrate;
• forming a lower source/drain (S/D) under the fin structure;
• forming a lower spacer, a gate pattern and an upper spacer surrounding a lower sidewall region, a center sidewall region and an upper sidewall region, respectively;
• forming an upper S/D on an upper surface of the fin structure so that the lower S/D, the fin structure and the upper S/D are vertically stacked on each other;
• forming a lower S/D electrode, an upper S/D electrode and a gate electrode electrically connected to the lower S/D, the upper S/D and the gate pattern, respectively;
• forming a blocking layer to cover the upper S/D, the lower S/D electrode, the upper S/D electrode and the gate electrode;
• forming a sacrificial pattern on the blocking layer and between the gate electrode and the lower S/D electrode, the sacrificial pattern having a first thickness and a first width;
• forming a capping layer on the sacrificial pattern to cover the sacrificial pattern;
• and
• forming an air gap by removing the sacrificial pattern through the capping layer,
• wherein the air gap is formed between the gate electrode and the lower S/D electrode and has the first thickness and the first width.