VTFET devices utilizing low temperature selective epitaxy
AssigneeInternational Business Machines Corporation
InventorsHemanth Jagannathan, Shogo Mochizuki
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Abstract
Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
Claims16
A method for forming a semiconductor structure comprising:
- providing a substrate comprising a first surface comprising single crystalline silicon and at least one additional surface comprising a dielectric material;
- epitaxially growing a silicon layer with a dopant at a temperature less than 500° C. on the substrate to form a single crystalline silicon on the first surface and a polysilicon/amorphous silicon on the additional surface, wherein the single crystalline silicon on the first surface and the polysilicon/amorphous silicon comprise a boundary therebetween, wherein a shape of the boundary is multifaceted;
- and
- exposing the epitaxially grown silicon layer to an etchant comprising HCl and germane at a temperature less than 500° C. to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
A method of forming a top source or drain region in a VTFET device, the method comprising:
- positioning a semiconductor substrate including a partial VTFET structure in an epitaxially deposition chamber, the partial VTFET structure comprising a substrate, a bottom doped source or drain region, a vertically oriented channel region extending from the bottom doped source or drain region, a gate stack over the channel region and between a bottom spacer overlying a portion of the bottom doped source and drain region and a top spacer, wherein a deposition surface of the partial VTFET structure includes a dielectric material and a topmost portion of the channel region;
- applying first source gasses for deposition of a material layer to the deposition surface at a temperature of less than 500° C., the first source gases comprising a phosphorous containing gas and a silicon containing gas selected from the group consisting of SiH4, Si2H6, Si3H8 and Si4H10, wherein a doped polysilicon/amorphous silicon layer is formed on the dielectric material and a doped single crystalline silicon layer is formed on the exposed topmost portion of the channel region;
- applying second source gasses for surface modification and etching, the second source gasses comprising HCl and germane, wherein the surface modification selectively diffuses germanium atoms into a portion of the polysilicon/amorphous silicon to render the germanium atom diffused portion removable upon contact with the HCl etchant so as to selectively remove the portion of the doped polysilicon/amorphous silicon layer relative to the doped single crystalline silicon and form the top source or drain region in the VTFET device.
Dependencies are inferred from the claim text.