Avalanche energy handling capable III-nitride transistors

A semiconductor device, comprising:

• a drain terminal of the semiconductor device;
• a gate terminal of the semiconductor device;
• a source terminal of the semiconductor device;
• a gallium nitride field effect transistor (GaN FET);
• an overvoltage clamping component, a first end of said overvoltage clamping component being electrically coupled to a drain node of said GaN FET and said drain terminal;
• and
• a voltage dropping component, a first end of said voltage dropping component being electrically coupled to a second end of said overvoltage clamping component, a second end of said voltage dropping component being electrically coupled to one of the gate terminal and the source terminal for an off-state bias potential, wherein:
• said GaN FET is a depletion mode GaN FET;
• a source node of said GaN FET is electrically coupled to a drain node of an n-channel metal oxide semiconductor (NMOS) transistor;
• a gate node of said GaN FET is electrically coupled to a source node of said NMOS transistor;
• and
• said second end of said voltage dropping component is electrically coupled to a gate node of said NMOS transistor.

A semiconductor device, comprising:

• a drain terminal of the semiconductor device;
• a gate terminal of the semiconductor device;
• a source terminal of the semiconductor device;
• a gallium nitride field effect transistor (GaN FET);
• an overvoltage clamping component, a first end of said overvoltage clamping component being electrically coupled to a drain node of said GaN FET and said drain terminal;
• and
• a voltage dropping component, a first end of said voltage dropping component being electrically coupled to a second end of said overvoltage clamping component, a second end of said voltage dropping component being electrically coupled to one of the gate terminal and the source terminal for an off-state bias potential, wherein said voltage dropping component is a metal oxide semiconductor (MOS) transistor.

A semiconductor device, comprising:

• a drain terminal of the semiconductor device;
• a gate terminal of the semiconductor device;
• a source terminal of the semiconductor device;
• a gallium nitride field effect transistor (GaN FET);
• an overvoltage clamping component, a first end of said overvoltage clamping component being electrically coupled to a drain node of said GaN FET and said drain terminal, wherein said overvoltage clamping component includes a plurality of diodes electrically coupled in series and wherein the plurality of diodes are formed in a low-defect layer comprising gallium nitride and a barrier layer comprising AlxGa1-xN, said GaN FET being disposed in a portion of said low-defect layer and said barrier layer;
• and
• a voltage dropping component, a first end of said voltage dropping component being electrically coupled to a second end of said overvoltage clamping component, a second end of said voltage dropping component being electrically coupled to one of the gate terminal and the source terminal for an off-state bias potential.

A semiconductor device, comprising:

• a drain terminal of the semiconductor device;
• a gate terminal of the semiconductor device;
• a source terminal of the semiconductor device;
• a gallium nitride field effect transistor (GaN FET);
• an overvoltage clamping component, a first end of said overvoltage clamping component being electrically coupled to a drain node of said GaN FET and said drain terminal, wherein said overvoltage clamping component includes a plurality of diodes electrically coupled in series and wherein the plurality of diodes are formed in a barrier layer comprising AlxGa1-xN and a metal gate layer, said GaN FET being disposed in a portion of said barrier layer and having a metal gate of said metal gate layer;
• and
• a voltage dropping component, a first end of said voltage dropping component being electrically coupled to a second end of said overvoltage clamping component, a second end of said voltage dropping component being electrically coupled to one of the gate terminal and the source terminal for an off-state bias potential.

A semiconductor device, comprising:

• a drain terminal of the semiconductor device;
• a gate terminal of the semiconductor device;
• a source terminal of the semiconductor device;
• a gallium nitride field effect transistor (GaN FET);
• an overvoltage clamping component, a first end of said overvoltage clamping component being electrically coupled to a drain node of said GaN FET and said drain terminal;
• and
• a voltage dropping component, a first end of said voltage dropping component being electrically coupled to a second end of said overvoltage clamping component, a second end of said voltage dropping component being electrically coupled to one of the gate terminal and the source terminal for an off-state bias potential, wherein said voltage dropping component is a resistor and wherein said resistor has a resistor body in a two-dimensional electron gas in a low-defect layer comprising gallium nitride, said GaN FET being disposed in a portion of said low-defect layer and having a channel conductive layer in said two-dimensional electron gas.