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US 9,865,716 B2Granted
System and method for a vertical tunneling field-effect transistor cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHarry Hak-Lay Chuang, Ming Zhu
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Abstract
A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.
Claims20
A method for forming a field effect transistor (FET), the method comprising:
- forming a protrusion on a surface of a substrate;
- doping a lower portion of the protrusion and a portion of the substrate with a first dopant to form a drain region of a transistor, wherein the drain region extends beyond the protrusion in a first direction and a second direction opposite the first direction;
- doping an upper portion of the protrusion with a second dopant to form a source region of the transistor, wherein the first and second dopants are of opposite types;
- forming a transistor gate to have a planar portion and a gating surface,
- wherein the gating surface surrounds a portion of the protrusion between the lower and upper portions of the protrusion,
- wherein the planar portion is parallel to the surface of the substrate and located directly above the doped portion of the substrate and directly above a trench isolation feature disposed within the substrate, the trench isolation feature extending into a region of the substrate below the drain region, and
- wherein an oxide layer is disposed between a gate dielectric of the planar portion and the trench isolation feature and further between the gate dielectric of the planar portion and the doped portion of the substrate;
- and
- forming a source contact connected to the source region, a drain contact connected to the drain region, and a gate contact connected to the planar portion of the transistor gate, the drain contact being closer to the source contact than to the gate contact.
6 more elements
A semiconductor device comprising:
- a protrusion formed over a substrate;
- a drain region formed over the substrate, wherein the drain region includes a lower portion of the protrusion and a doped portion of the substrate that extends beyond the protrusion in a first direction and a second direction opposite the first direction, and wherein the doped portion of the substrate that extends in the first direction is contacted by a drain contact;
- a source region formed in an upper portion of the protrusion, wherein the source region is contacted by a source contact, and the source region and the drain region have opposite types of dopants;
- a channel region formed between the lower and upper portions of the protrusion;
- and
- a transistor gate having a gating surface and a planar portion,
- wherein the gating surface surrounds the channel region,
- wherein the planar portion is located directly above the doped portion of the substrate that extends in the second direction and directly above a trench isolation feature within the substrate, the trench isolation feature extending into a region of the substrate below the drain region,
- wherein an oxide layer is disposed between a gate dielectric of the planar portion and the trench isolation feature,
- wherein the planar portion is contacted by a gate contact, and
- wherein, from a top view, the drain contact is closer to the source contact than to the gate contact.
8 more elements
A semiconductor device comprising:
- a first tunneling field effect transistor (TFET) and a second TFET formed over a substrate, wherein the first and second TFETs further includes, respectively:
- a protrusion formed over the substrate;
- a drain region formed over the substrate, wherein the drain region includes a planar drain portion and a raised drain portion, the raised drain portion is a lower portion of the protrusion, and the planar drain portion further comprises a first portion and a second portion that each extend beyond the raised drain portion, wherein the first portion is contacted by a drain contact;
- a source region formed in an upper portion of the protrusion, wherein the source region and the drain region have opposite types of dopants and the source region is contacted by a source contact;
- and
- a transistor gate with a planar gate portion and a gating surface, the gating surface surrounding both a portion of the source region and a portion of the raised drain portion, and
- wherein the planar gate portion of the first TFET and the planar gate portion of the second TFET are formed from a single planar structure, and the single planar structure is contacted by a gate contact and is located directly above a trench isolation feature within the substrate and further directly above the second portion of the planar drain portion with an oxide layer, the trench isolation feature extending into a region of the substrate below the drain region, and wherein the oxide layer is disposed between a gate dielectric of the planar drain portion and the trench isolation feature.
4 more elements
Dependencies are inferred from the claim text.