Methods to integrate SONOS into CMOS flow

A method comprising:

• depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a transistor, the dielectric stack including a first oxide layer overlying the surface of the substrate, a nitride layer overlying the first oxide layer and a second oxide layer overlying the nitride layer;
• forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor;
• etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the nitride layer in S/D regions of the transistor;
• implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the transistor;
• and
• depositing a spacer layer over the gate of the transistor and the surface of the substrate, and anisotropically etching the spacer layer to form spacers adjacent sidewalls of the gate of the transistor, wherein depositing and etching the spacer layer to form spacers is done prior to forming the mask over the dielectric stack.

A method comprising:

• forming a dielectric stack including a tunneling layer overlying a surface of a substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer;
• forming a gate of a transistor over the dielectric stack;
• forming spacers adjacent sidewalls of the gate;
• forming over the spacers, gate and the dielectric stack a mask exposing source and drain (S/D) regions of the transistor;
• etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a portion of the charge-trapping layer in S/D regions of the transistor;
• and
• implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the gate of the transistor.