FinFET having a non-uniform fin
AssigneeSTMicroelectronics S.r.l.
InventorQing Liu
Life of this patent
Estimating the term…
Abstract
A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.
Claims21
A FinFET, comprising:
- a silicon substrate having an oxide layer buried therein;
- a raised silicon source region overlying the silicon substrate;
- a raised silicon drain region overlying the silicon substrate;
- a strained silicon fin having, as a first portion, a channel region that extends between the raised source and drain regions, the channel region having a first fin width, a second fin portion in the source region, the second fin portion having a second fin width that is smaller than the first fin width, and a third fin portion in the drain region, the third fin portion having a third fin width that is substantially equal to the second fin width;
- and
- a metal gate structure that wraps around at least three sides of the strained silicon fin to control current flow in the channel region.
A FinFET, comprising:
- a raised source region;
- a raised drain region;
- a fin extending from the raised source region to the raised drain region, the fin having a non-uniform fin width that varies along a length of the fin, a channel region of the fin being approximately twice as thick as portions of the fin outside the channel region;
- and
- a gate that wraps around three sides of the channel region of the fin, the gate configured to control current flow within the channel region, between the raised source region and the raised drain region.
A device, comprising:
- a silicon substrate;
- a buried oxide layer in the silicon substrate;
- a strained silicon fin above the buried oxide layer, the strained silicon fin including a wide portion having a first fin width and a narrow portion having a second fin width;
- a top oxide layer covering the strained silicon fin;
- a gate structure adjacent to the strained silicon fin, the gate structure including a metal gate electrode and a gate oxide adjacent to the gate electrode;
- and
- raised source and drain regions adjacent to the strained silicon fin, the wide portion corresponding to a channel region, the narrow portion corresponding to the source and drain regions.
A device, comprising:
- a silicon substrate;
- a buried oxide layer in the silicon substrate;
- a strained silicon fin above the buried oxide layer, the strained silicon fin including a wide portion having a first fin width and a narrow portion having a second fin width, the wide portion and the narrow portion having substantially a same degree of strain;
- a top oxide layer covering the strained silicon fin;
- a gate structure adjacent to the strained silicon fin, the gate structure including a metal gate electrode and a gate oxide adjacent to the gate electrode;
- and
- raised source and drain regions adjacent to the strained silicon fin.
A FinFET, comprising:
- a raised source region;
- a raised drain region;
- a fin extending from the raised source region to the raised drain region, the fin having a non-uniform fin width that varies along a length of the fin, portions of the fin outside a channel region of the fin having a substantially uniform distribution of dopants;
- and
- a gate that wraps around three sides of the channel region of the fin, the gate configured to control current flow within the channel region, between the raised source region and the raised drain region.
Dependencies are inferred from the claim text.