Single and double diffusion breaks on integrated circuit products comprised of FinFET devices

An integrated circuit product, comprising:

• a plurality of FinFET devices;
• a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, wherein said SDB isolation structure comprises a conformal liner layer comprising a first insulating material that is positioned on and in contact with said semiconductor substrate within said first trench, a second layer of a second insulating material different than said first insulating material, and a conductive material formed above said second layer;
• a first sidewall spacer that contacts and engages opposite sidewall surfaces of said conformal liner layer of said SDB isolation structure, wherein an uppermost surface of said SDB isolation structure has a height greater than a lowermost surface of said first sidewall spacer;
• a double diffusion break (DDB) isolation structure positioned in a second trench defined in said semiconductor substrate between third and fourth active regions;
• and
• second and third sidewall spacers, said second sidewall spacer engaging and contacting a first sidewall surface of said DDB isolation structure, said third sidewall spacer engaging and contacting a second sidewall surface of said DDB isolation structure opposite said first sidewall surface, wherein an uppermost surface of said DDB isolation structure has a height greater than lowermost surfaces of said second and third sidewall spacers.

An integrated circuit product, comprising:

• a plurality of FinFET devices;
• a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, wherein said SDB isolation structure comprises an insulating material positioned in a bottom of said first trench and a conductive material positioned within said first trench vertically above said insulating material;
• a first sidewall spacer that contacts and engages opposite sidewall surfaces of said conformal liner layer of said SDB isolation structure, wherein an uppermost surface of said SDB isolation structure has a height greater than a lowermost surface of said first sidewall spacer, and said first sidewall spacer contacts opposite sidewall surfaces of said conductive material;
• a double diffusion break (DDB) isolation structure positioned in a second trench defined in said semiconductor substrate between third and fourth active regions;
• and
• second and third sidewall spacers, said second sidewall spacer engaging and contacting a first sidewall surface of said DDB isolation structure, said third sidewall spacer engaging and contacting a second sidewall surface of said DDB isolation structure opposite said first sidewall surface, wherein an uppermost surface of said DDB isolation structure has a height greater than lowermost surfaces of said second and third sidewall spacers.