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US 9,865,698 B2Granted
Semiconductor device blocking leakage current and method of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-Kwan Yu, Kooktae Kim, Chanjin Park, Dongsuk Shin, Youngdal Lim, Sahwan Hong
Life of this patent
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Abstract
A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.
Claims16
A semiconductor device, comprising:
- a gate assembly disposed on a device isolation layer;
- a gate spacer disposed on a side surface of the gate assembly;
- a contact assembly disposed on the gate spacer;
- an air gap disposed between the device isolation layer and the contact assembly;
- a first spacer capping layer disposed between the gate spacer and the air gap,
- wherein the first spacer capping layer has an etch selectivity with respect to the gate spacer, and
- a second spacer capping layer disposed between the gate spacer and the first spacer capping layer,
- wherein the second spacer capping layer has an etch selectivity with respect to the first spacer capping layer,
- wherein the first spacer capping layer surrounds the air gap such that the contact assembly including a conductive material is spaced apart from the air gap by the first spacer capping layer including an insulating material.
6 more elements
A semiconductor device, comprising:
- a substrate comprising a first fin body and a second fin body spaced apart from the first fin body;
- a device isolation layer disposed between the first fin body and the second fin body;
- a gate assembly disposed on the substrate;
- a gate spacer disposed on a side surface of the gate assembly;
- a contact assembly disposed on the gate spacer;
- an air gap disposed between the first fin body and the second fin body;
- a first spacer capping layer surrounding the air gap and having an etch selectivity with respect to the gate spacer, and
- a second spacer capping layer disposed between the gate spacer and the first spacer capping layer,
- wherein the second spacer capping layer has an etch selectivity with respect to the first spacer capping layer,
- wherein the first spacer capping layer surrounds the air gap such that the contact assembly including a conductive material is spaced apart from the air gap by the first spacer capping layer including an insulating material.
7 more elements
A semiconductor device, comprising;
- a plurality of gate assemblies disposed on a device isolation layer;
- a plurality of gate spacers disposed on side surfaces of the gate assemblies;
- a plurality of contact assemblies disposed on the gate spacers;
- a plurality of air gaps disposed between the gate spacers;
- a plurality of first spacer capping layers disposed between the gate spacers and the air gaps, wherein the first spacer capping layers have an etch selectivity with respect to the gate spacers,
- wherein an uppermost end of the first spacer capping layers is higher than an uppermost end of the air gaps, and
- a plurality of second spacer capping layers disposed between the gate spacers and the first spacer capping layers,
- wherein the second spacer capping layers have an etch selectivity with respect to the first spacer capping layers,
- wherein the first spacer capping layers surround the air gaps such that the contact assemblies including a conductive material are spaced apart from the air gaps by the first spacer capping layers including an insulating material.
6 more elements
Dependencies are inferred from the claim text.