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US 9,865,695 B2Granted
High-voltage transistor architectures, processes of forming same, and systems containing same
AssigneeIntel Corporation
InventorsWalid M. Hafez, Chia-Hong Jan, Anisur Rahman
Life of this patent
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Abstract
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
Claims16
A system comprising:
- a first device, in a first region of a semiconductive substrate, which comprises:
- a channel in the semiconductive substrate;
- a gate electrode on the channel;
- a source implant on a first side of the gate electrode and a drain implant on a second side of the gate electrode;
- a drain well in the semiconductive substrate that forms a junction with the channel;
- a salicide source contact pad on the semiconductive substrate;
- a salicide drain contact pad on the drain well, wherein the salicide drain contact pad is located farther from the second side than the source contact pad is located from the first side;
- and
- an interlayer dielectric layer (ILD0) on the salicide drain contact pad and the drain well;
- a second device in a second region of the semiconductive substrate;
- and
- a third device in a third region of the semiconductive substrate;
- wherein the first device is configured to operate at a voltage higher than the second device;
- wherein the third device is configured to operate at a voltage lower than the second device.
11 more elements
A system comprising:
- a first device, in a first region of a semiconductive substrate, which comprises:
- a channel in a semiconductive substrate;
- a gate electrode on the channel;
- a source implant on a first side of the gate electrode and a drain implant on a second side of the gate electrode;
- a drain well in the semiconductive substrate that forms a junction with the channel;
- a salicide source contact pad in the semiconductive substrate;
- a salicide drain contact pad in the drain well, wherein the salicide drain contact pad is located farther from the second side than the source contact pad is located from the first side;
- and
- an interlayer dielectric layer (ILD0);
- a second device in a second region of the semiconductive substrate;
- and
- a third device in a third region of the semiconductive substrate;
- wherein the first device is configured to operate at a voltage higher than the second device;
- wherein the third device is configured to operate at a voltage lower than the second device.
11 more elements
Dependencies are inferred from the claim text.