Nanowire transistors having multiple threshold voltages
AssigneeGlobalfoundries Inc.
InventorsXusheng Wu, John Zhang, Jiehui Shu
Life of this patent
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Abstract
Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.
Claims20
A method of forming a structure, comprising:
- depositing a first sacrificial layer on a semiconductor substrate, the first sacrificial layer having a first thickness in a first region of the substrate and a second thickness greater than the first thickness in a second region of the substrate;
- depositing a first semiconductor layer on the first sacrificial layer;
- depositing a second sacrificial layer on the first semiconductor layer, wherein a thickness of the second sacrificial layer within the first region of the substrate is substantially equal to the first thickness, and a thickness of the second sacrificial layer within the second region of the substrate is substantially equal to the second thickness;
- and
- depositing a second semiconductor layer on the second sacrificial layer.
A method of forming a structure, comprising:
- depositing a first sacrificial layer on a semiconductor substrate, the first sacrificial layer having a first thickness;
- forming a first blocking mask over the first sacrificial layer within a first region of the substrate;
- depositing additional first sacrificial layer material within the second region to form a first sacrificial layer within the second region having a second thickness greater than the first thickness;
- depositing a first semiconductor layer on the first sacrificial layer;
- depositing a second sacrificial layer on the first semiconductor layer, the second sacrificial layer having the first thickness;
- forming a second blocking mask over the second sacrificial layer within the first region of the substrate;
- depositing additional second sacrificial layer material within the second region to form a second sacrificial layer within the second region having the second thickness;
- depositing a second semiconductor layer on the second sacrificial layer;
- selectively etching the first and second sacrificial layers to form first cavities within the first region and second cavities within the second region;
- depositing a dielectric layer on the first semiconductor layer within the first cavities and on the second semiconductor layer within the second cavities;
- and
- depositing a work function metal layer on the dielectric layer within the first cavities and on the dielectric layer within the second cavities, wherein the work function metal layer substantially fills the first and second cavities.
Dependencies are inferred from the claim text.