Semiconductor memory device

A semiconductor memory device, including a memory cell array, the memory cell array including a plurality of memory cells, the memory cell array comprising:

• a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction;
• a plurality of second conductive layers that are stacked in the first direction above the substrate and extend in the second direction, the plurality of second conductive layers being adjacent to the plurality of the first conductive layers in a third direction intersecting the first direction and the second direction;
• a third conductive layer extending in the first direction;
• a first variable resistance film provided at intersections of the plurality of first conductive layers and the third conductive layer;
• a second variable resistance film provided at intersections of the plurality of second conductive layers and the third conductive layer;
• a first select transistor disposed closer to the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the third conductive layer;
• a fourth conductive layer that extends in the third direction and is connected to a lower end of the third conductive layer via the first select transistor;
• and
• a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the third conductive layer.