Memory cell structure with resistance-change material and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJean-Pierre Colinge, Carlos H. Diaz
Life of this patent
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Abstract
Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy.
Claims20
A semiconductor structure, comprising:
- a substrate;
- a nanowire structure formed over the substrate;
- a drain structure formed over the nanowire structure;
- and
- a memory cell structure formed over the drain structure, wherein the memory cell structure comprises:
- a first electrode layer formed over the substrate;
- a resistance-change material layer formed over the first electrode layer;
- and
- a second electrode layer formed over the resistance-change material layer,
- wherein the resistance-change material layer comprises a semimetal or a semimetal alloy and is positioned between the first electrode layer and the second electrode layer, and the resistance-change material layer has a melting point in a range of about 150° C. to about 300° C.
A semiconductor structure, comprising:
- a substrate;
- a nanowire structure formed over the substrate;
- a drain structure formed on the nanowire structure;
- a first electrode layer formed over the drain structure;
- a resistance-change material layer formed over the first electrode layer;
- and
- a second electrode layer formed over the resistance-change material layer,
- wherein the resistance-change material layer is a semimetal layer or a semimetal alloy layer and is positioned between the first electrode layer and the second electrode layer.
A method for manufacturing a memory cell, comprising:
- forming a drain structure over a nanowire structure over a substrate;
- forming a first electrode layer over the drain structure;
- forming a dielectric layer over the first electrode layer;
- forming a trench in the dielectric layer;
- forming a resistance-change material layer in the trench;
- forming a second electrode layer over dielectric layer to cover the resistance-change material layer, wherein the resist-change material layer is a semimetal layer or a semimetal alloy layer and is positioned between the first electrode layer and the second electrode layer,
- wherein a grain size of the resistance-change material layer is enlarged when a writing current pulse is applied to the resistance-change material layer, and the grain size of the resistance-change material layer is shrunken when an erasing current pulse is applied to the resistance-change material layer, and a slope of a falling edge of the writing current pulse is greater than a slope of a falling edge of the erasing current pulse.
Dependencies are inferred from the claim text.