Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application

A method of forming a device comprising:

• providing a substrate defined with at least first and second regions, wherein the first region is a memory region for accommodating at least one memory cell, the second region is a logic region for accommodating at least one logic component;
• providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate, comprising
• wherein the plurality of ILD levels comprises
• an ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx,
• an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1, and
• the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2,
• forming a first dielectric layer and forming a second upper dielectric layer over the first and second regions covering the first dielectric layer, wherein the first and second dielectric layers comprise low-k dielectric layers, and
• patterning the second dielectric layer to form a trench opening in the first region, wherein the trench opening extends from a top surface of the second dielectric layer to a top surface of the metal line in the metal level Mx in the first region which-accommodates the bottom electrode;
• forming a two-terminal device element in between metal level Mx and via level Vx+1 in the first region, wherein the two-terminal device element is a storage element of the MRAM cell and comprises a device layer coupled in between first and second terminals, wherein the first terminal is a bottom electrode and is in direct contact with the metal line in metal level Mx of the first region, the second terminal is a top electrode and is formed on a top surface of the device layer, and the device layer is a MTJ stack of the MRAM cell;
• forming a dual damascene interconnect over the second region in the second ILD level, wherein the dual damascene interconnect comprises a metal line in metal level Mx+1 and via contact in via level Vx in the second region;
• and
• forming dual damascene interconnects in the third ILD level over the first and second regions, wherein a dual damascene interconnect includes a metal line in metal level Mx+2 and a via contact in via level Vx+1, and wherein the dual damascene interconnect in the first region is coupled to the two-terminal device element and the dual damascene interconnect in the second region is formed over and is coupled to the dual damascene interconnect in the second ILD level.

A device comprising:

• a substrate defined with at least first and second regions;
• a plurality of interlevel dielectric (ILD) levels having tight pitch disposed over the first and second regions of the substrate, wherein the plurality of ILD levels comprises
• a first dielectric liner,
• a second upper dielectric liner over the first and second regions covering the first dielectric liner,
• a trench opening in the second dielectric liner,
• an ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx,
• an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes a via level Vx and a metal level Mx+1, and
• the next overlying ILD level corresponds to a third ILD level includes a via level Vx+1 and a metal level Mx+2;
• a two-terminal device element disposed in between the metal level Mx and the via level Vx+1 in the first region, wherein the two-terminal device element comprises a device layer coupled in between the first and second terminals, wherein the first terminal is in direct contact with a metal line in the metal level Mx of the first region and the second terminal is formed on a top surface of the device layer, and wherein the device layer is a MTJ stack of a MRAM cell, and wherein a total height of the MTJ stack with top and bottom electrodes is greater than a height of a via contact in the via level Vx and is shallower or same as a total height of a metal line in the metal level Mx+1 and the via contact in the via level Vx;
• a dual damascene interconnect disposed over the second region in the second ILD level, wherein the dual damascene interconnect comprises a metal line in the metal level Mx+1 and the via contact in the via level Vx in the second region;
• and
• dual damascene interconnects disposed in the third ILD level over the first and second regions, wherein a dual damascene interconnect includes a metal line in the metal level Mx+2 and a via contact in the via level Vx+1, and wherein the dual damascene interconnect in the first region is coupled to the two-terminal device element and the dual damascene interconnect in the second region is disposed over and is coupled to the dual damascene interconnect in the second ILD level.