Systems and methods for testing and packaging a superconducting chip
AssigneeD-Wave Systems Inc.
InventorPaul I. Bunyk
Life of this patent
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Abstract
Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.
Claims28
A method of testing and packaging a superconducting chip, wherein the superconducting chip includes at least one material that superconducts below a critical temperature, the method comprising:
- forming a first set of superconducting solder bumps on the superconducting chip;
- superconductively electrically coupling the superconducting chip to a testing module via the first set of superconducting solder bumps to form a testing assembly;
- cooling the testing assembly to a first temperature below the critical temperature such that the superconducting chip superconducts;
- testing electrical properties of the superconducting chip while the superconducting chip superconducts;
- removing the superconducting chip from the testing assembly, wherein removing the superconducting chip from the testing assembly includes decoupling the superconducting chip from the testing module via the first set of superconducting solder bumps;
- forming a second set of superconducting solder bumps on a chip packaging module;
- and
- after removing the superconducting chip from the testing assembly, superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps.
A method of testing and packaging a superconducting chip, wherein the superconducting chip includes at least one material that superconducts below a critical temperature, the method comprising:
- forming a first set of superconducting solder bumps on a testing module;
- superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps to form a testing assembly;
- cooling the testing assembly to a first temperature below the critical temperature such that the superconducting chip superconducts;
- testing electrical properties of the superconducting chip while the superconducting chip superconducts;
- removing the superconducting chip from the testing assembly, wherein removing the superconducting chip from the testing assembly includes decoupling the superconducting chip from the testing module via the first set of superconducting solder bumps;
- forming a second set of superconducting solder bumps on a chip packaging module;
- and
- after removing the superconducting chip from the testing assembly, superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps.
A method of forming a superconductive interconnection structure, the method comprising:
- depositing a superconductive bonding pad;
- depositing a pillar of under-bump metal (“UBM”) on a portion of the superconductive bonding pad;
- depositing a bump of superconductive solder on the pillar of UBM;
- and
- depositing a layer of superconductive material over the pillar of UBM and a portion of the superconductive bonding pad not covered by the pillar of UBM such that the layer of superconductive material is interposed between the pillar of UBM, a portion of the superconductive bonding pad not covered by the pillar of UBM, and the bump of superconductive solder;
- wherein the portion of the superconductive bonding pad on which the UBM is deposited is less than the entirety of a surface of the superconductive bonding pad;
- and
- wherein depositing a layer of superconductive material over the pillar of UBM and a portion of the superconductive bonding pad not covered by the pillar of UBM includes depositing a layer of tin over the pillar of UBM and a portion of the superconductive bonding pad not covered by the pillar of UBM.
Dependencies are inferred from the claim text.