Interconnect structure for stacked device and method

A method comprising:

• bonding a first semiconductor substrate to a second semiconductor substrate, wherein a first dielectric layer and a second dielectric layer are disposed between the first and second semiconductor substrates, wherein a first interconnection feature and a conductive plug are disposed within the first dielectric layer and a second interconnection feature is disposed within the second dielectric layer, wherein the conductive plug physically contacts the first interconnection feature and the first semiconductor substrate;
• patterning the first semiconductor substrate to form a first trench that extends through the first semiconductor substrate to expose the conductive plug;
• forming a patterned mask layer within the first trench;
• removing a portion of the first dielectric layer and a portion of the second dielectric layer through the first trench to form a second trench extending to the second interconnection feature;
• removing the patterned mask layer from the first trench to expose the conductive plug;
• and
• forming a conductive material within the first trench and the second trench such that conductive material physically contacts the conductive plug and the second interconnection feature.

A method comprising:

• providing a first semiconductor element, the first semiconductor element including:
• a first substrate;
• a first inter-level dielectric (ILD) layer over the first substrate;
• a first interconnection feature in the first ILD layer;
• and
• a conductive plug in the first ILD layer, wherein the conductive plug connecting with the first substrate and the first interconnection feature, wherein the conductive plug physically contacts the first interconnection feature and the first substrate;
• bonding the first semiconductor element on a second semiconductor element, wherein the second semiconductor element comprises:
• a second substrate;
• a second inter-level dielectric (ILD) layer over the second substrate;
• and
• a second interconnection feature in the second ILD layers;
• forming a substrate trench in the first substrate to expose the conductive plug and the first ILD layer;
• depositing a dielectric isolation layer over the first substrate and sidewalls of the substrate trench;
• removing the dielectric isolation layer from a bottom of the substrate trench to expose the first ILD layer;
• forming a deep-interconnection-trench (DIT) pattern mask in the substrate trench;
• etching the first ILD layer and the second ILD layer through the DIT pattern mask to form a first DIT connecting to the second interconnection feature;
• removing the patterned mask to form a second DIT having the substrate trench as an upper portion and the first DIT as a lower portion;
• and
• filling the second DIT with conductive materials to form a conductive deep plug to couple the first and second semiconductor elements.