Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate

#This invention relates to solid state image sensors, and more specifically to solid state image sensors formed on n-type substrates and having an electronic Global Shutter (GS).

#Solid-state image sensors are used in, for example, video cameras, and are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a liquid crystal display (LCD).

#More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography, coupled with advanced signal-processing algorithms, sets the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array.

#These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:

#FIGS. 1(A) and 1(B) are cross-sectional and pseudo exploded perspective views showing a partial GS CMOS image sensor including one pixel formed in accordance with a simplified embodiment of the present invention;

#FIG. 2(A) is a hybrid block/circuit diagram showing a GS CMOS image sensor according to another embodiment of the present invention;

#The present invention relates to an improvement in CMOS image sensors, and more particularly to improvements in global shutter (GS) CMOS image sensors for use in machine vision and in other high resolution applications that require low noise global shutter operation. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. The terms “coupled” and “connected”, which are utilized herein, are defined as follows. The term “connected” is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term “coupled” is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). In addition, relative terms such as “upper”, “uppermost”, “above”, “below”, “downward”, “vertical”, “vertically”, “horizontally” and “under” are intended to denote relative differences, and not intended to be literally interpreted unless otherwise specified. The terms “n-doped” and “n-type” refer to semiconductor material having a predominantly n-type doping profile (i.e., a higher concentration of n-type dopant(s) than p-type dopant(s)), whereas the terms “p-doped” and “p-type” refer to semiconductor material having a predominantly p-type doping profile (i.e., a higher concentration of p-type dopant(s) than n-type dopant(s)). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

#FIG. 1(A) shows a partial CMOS global shutter (GS) image sensor 100 formed on a semiconductor substrate 101 including a simplified pixel 110. Pixel 110 is understood as being one of many pixels that collectively form GS image sensor 100 in the manner set forth below. Note that the details of pixel 110 shown in these figures are intended to depict novel aspects of image sensor 100. That is, FIGS. 1(A) and 1(B) illustrate only the structures of image sensor 100 that are considered novel with respect to conventional approaches, and additional structures required to implement a functional pixel circuit are omitted for clarity. Specifically, a second storage element (e.g., the floating diffusion discussed below) and pixel control elements (e.g., additional transfer gate, reset, source-follower and select transistors needed to allow pixel 110 to capture, store and readout image information) are omitted from FIG. 1(A) to more clearly depict the novel structures and features, and because these control portions may be implemented using a number of different circuit arrangements in combination with the depicted novel structures and features.

#Referring to FIG. 1(A), substrate 101 includes a p-type vertical barrier implant 101-3 sandwiched between an n-doped bulk substrate 101-1 and an n-doped region 101-21 in which pixel 110 is partially formed. In one embodiment, substrate 101 includes an n-doped epitaxial silicon (n-epi) layer 101-2 formed on bulk substrate 101-1. In an exemplary embodiment, n-doped bulk substrate 101-1 comprises monocrystalline silicon having one or more of an n-type doping concentration in the range of 1×1018 to 1×1020 atoms/cm3 or a conductivity in the range of 1 mOhm/cm to 100 mOhm/cm. As indicated at the right edge of FIG. 1(A), epitaxial layer 101-2 is formed as an integral layer on upper surface 101-1U of bulk substrate 101-1, and includes a designated n-doped region 101-21, an intermediate p-doped sinker implant region 101-22 that surrounds n-doped region 101-21, an exemplary surrounding n-doped region 101-23 that surrounds p-doped sinker implant region 101-22, p-type vertical barrier implant region 101-3, and an optional additional n-epi region 101-24 disposed between p-type vertical barrier implant region 101-3 and bulk substrate 101-1. In an exemplary embodiment, intrinsic portions of n-epi layer 101-2 (e.g., n-doped regions 101-21, 101-23 and 101-24) have one or more of an n-type doping concentration in the range of 1×1013 to 5×1015 atoms/cm3 or a conductivity in the range of 10 kOhm/cm to 5 Ohm/cm. In one embodiment, p-type vertical barrier implant 101-3 and p-type sinker implant region 101-22 comprise p-doped epitaxial material having a p-type doping concentration in the range of 1×1014 to 5×1016 atoms/cm3, and are formed by diffusing one or more p-type dopants into corresponding portions of n-type epitaxial layer 101-2 using known techniques.