Semiconductor memory device and method for manufacturing same

#Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

#A memory device having a three-dimensional structure has been proposed in which memory holes are made in a stacked body in which electrode layers that function as control gates of memory cells are multiply stacked with insulating layers interposed between the electrode layers, and silicon bodies used to form channels are provided on the side walls of the memory holes with a charge storage film interposed between the silicon bodies and the side walls.

#In such a three-dimensional device, the memory holes and slits are made in the stacked body that includes the multiple layers of electrode layers and the multiple layers of insulating layers by, for example, RIE (Reactive Ion Etching). High shape controllability and dimensional controllability are desirable for the etching in such a case.

#FIG. 1 is a schematic perspective view of a memory cell array of an embodiment;

#FIGS. 2A and 2B are schematic cross-sectional views of a memory string of the embodiment;

#FIG. 3 is a schematic cross-sectional view of a memory cell of the embodiment;

#According to one embodiment, a semiconductor memory device includes a stacked body and a plurality of columnar portions. The stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

#Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals.

#FIG. 1 is a schematic perspective view of a memory cell array 1 of an embodiment. In FIG. 1, the insulating layers between the electrode layers, the insulating separation films, etc., are not shown for easier viewing of the drawings.