One-time-programming (OTP) memory cell with floating gate shielding

A memory cell with floating gate shielding, comprising:

• a pair of transistors arranged on a semiconductor substrate and electrically coupled in series, wherein the transistors comprise a floating gate configured to store a bit of data;
• an interconnect structure overlying the transistors, wherein the interconnect structure comprises interconnect layers of line features stacked upon one another, and further comprises via layers of via features interconnecting the line features between the interconnect layers;
• a shield arranged directly over the floating gate and comprising a feature of the interconnect or via layers;
• and
• a diffusion path for hydrogen ions extending from a top surface of the interconnect structure to the shield, wherein the diffusion path is line shaped and substantially orthogonal to a top surface of the floating gate, and wherein the shield is configured to block hydrogen diffusing along the diffusion path from reaching the floating gate.

A one-time programmable memory cell comprising:

• a semiconductor substrate comprising a first source/drain region, a second source/drain region, and a third source/drain region, wherein the second source/drain region is between the first and second source/drain regions, and wherein dangling bonds along a top surface of the semiconductor substrate are terminated by hydrogen;
• a select transistor comprising the first and second source/drain regions, and further comprising a select gate electrode, wherein the select gate electrode is over the semiconductor substrate, and wherein the select gate electrode is between and borders the first and second source/drain regions;
• a floating transistor comprising the second and third source/drain regions, and further comprising a floating gate electrode, wherein the floating gate electrode is over the semiconductor substrate, and wherein the floating gate electrode is between and borders the second and third source/drain regions;
• an interconnect structure covering the semiconductor substrate, the select transistor, and the floating transistor, wherein the interconnect structure comprises an ILD layer, a plurality of via layers, and a plurality of interconnect layers, and wherein the interconnect layers are alternatingly stacked with the via layers in the ILD layer;
• and
• a shield covering the floating gate electrode and comprising conductive features of the via layers and the interconnect layers, wherein the interconnect and via layers are limited to a periphery of the one-time programmable memory cell, except for a portion for the interconnect and via layers making up the shield, when the interconnect structure is viewed in profile.