Method of forming a device including a floating gate electrode and a layer of ferroelectric material

A method, comprising:

• providing a semiconductor structure, said semiconductor structure comprising a semiconductor substrate and a gate stack, said gate stack comprising a gate insulation material over said substrate, a floating gate electrode material over said gate insulation material, a ferroelectric transistor dielectric over said floating gate electrode material and a top electrode material over said ferroelectric transistor dielectric;
• performing a first patterning process, said first patterning process removing portions of said top electrode material and said ferroelectric transistor dielectric, portions of said top electrode material and said ferroelectric transistor dielectric that are not removed in said first patterning process forming an upper portion of a gate structure, portions of said floating gate electrode material and said gate insulation material that are not covered by said upper portion of said gate structure remaining in said semiconductor structure;
• forming a liner layer above said gate stack after performing said first patterning process;
• forming a mask layer above a portion of said liner layer above said upper portion of said gate structure;
• and
• performing a second patterning process after said first patterning process using said liner layer and said mask layer, said second patterning process removing portions of said first liner layer, said floating gate electrode material, and said gate insulation material not covered by said mask layer, portions of said floating gate electrode material and said gate insulation material that are not removed in said second patterning process forming a lower portion of said gate structure;
• wherein a projected area of said upper portion of said gate structure onto a plane that is perpendicular to a thickness direction of said substrate is smaller than a projected area of said lower portion of said gate structure onto said plane.