Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsQing Liu, Akira Ito
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Abstract
A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.
Claims20
A programmable cell, comprising:
- a fully depleted semiconductor-on-insulator substrate comprising a semiconductor layer, the semiconductor layer comprising a first doped source/drain region, a second doped source/drain region and a region comprising germanium, wherein the first doped source/drain region is coupled to a bit line and the second doped source/drain region is adjacent the region comprising germanium;
- a program gate disposed above the region comprising germanium and comprising a gate dielectric layer disposed below a gate conductor;
- and
- a word line gate disposed between the first doped source/drain region and the second source/drain region.
A programmable cell, comprising:
- a fully depleted semiconductor-on-insulator substrate comprising a semiconductor layer, the semiconductor layer comprising a first doped source/drain region, a second doped source/drain region and a region comprising germanium, wherein the region comprising germanium comprises silicon germanium region, wherein the silicon germanium region is 20 to 30 percent germanium;
- a program gate disposed above the region comprising germanium and comprising a gate dielectric layer disposed below a gate conductor;
- and
- a word line gate disposed between the first doped source/drain region and the second source/drain region.
A method of manufacturing a programmable cell, the method comprising:
- providing a fully depleted semiconductor-on-insulator substrate comprising a semiconductor layer, the semiconductor layer comprising a first doped source/drain region, a second doped source/drain region and a region comprising germanium;
- providing a bit line, wherein the first doped source/drain region is coupled to the bit line and the second doped source/drain region is adjacent the region comprising germanium;
- providing a word line gate between the first doped source/drain region and the second source/drain region;
- and
- providing a program gate above the region comprising germanium and comprising a gate dielectric layer disposed below a gate conductor.
A one-time programmable device, comprising:
- a semiconductor-on-insulator substrate;
- a first cell disposed on the semiconductor-on-insulator substrate and comprising a first gate disposed between a first doped source/drain region and a second doped source/drain region;
- a second cell disposed on the semiconductor-on-insulator substrate and comprising a second gate disposed between a third doped source/drain region and a fourth doped source/drain region;
- and
- a doped isolation region disposed between the second source/drain region and the fourth source/drain region, the doped isolation region being heavily doped with N type dopants and the second doped source/drain region and the fourth doped source/drain region being heavily doped with P type dopants.
Dependencies are inferred from the claim text.