Semiconductor device and semiconductor memory device

A semiconductor memory device comprising:

• a first word line;
• a first bit line and a second bit line;
• and
• a first memory cell including a first data holding circuit, a first transistor connected between the first data holding circuit and the first bit line, and a second transistor connected between the first data holding circuit and the second bit line,
• wherein each of the first and second transistors includes:
• a first region disposed in a first semiconductor region and connected to the first data holding circuit, the first region having a first conductivity type;
• a second region disposed in the first semiconductor region and connected to the first or second bit line, the second region having a second conductivity type;
• a first gate electrode above a first part of the first semiconductor region between the first region and the second region, the first gate electrode connected to the first word line;
• a first gate insulating layer between the first part and the first gate electrode;
• a third region having the first conductivity type below the second region;
• and
• a fourth region across the second region and the third region and including a first impurity.