US 9,865,604 B2 · Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

Claims10

Dependent claims

A semiconductor device comprising:

a first well region of a first conductivity type including a first part to a third part;
a first power feeding region of the first conductivity type;
and
a second well region of a second conductivity type including a fourth part,
wherein the first part and the second part are arranged to be adjacent to both sides of the fourth part in a first direction,
the third part has a shape extending in the first direction, and is arranged to be joined to the first part and the second part and be adjacent to the fourth part in a second direction intersecting with the first direction,
the first power feeding region supplies a predetermined voltage to the first part and the second part via the first well region, and
a size of the first power feeding region in the first direction is larger than a size of the first power feeding region in the second direction.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/277,723Filed 27 Sep 2016 · continuation

Priority

7 Jan 2016

Published

US 2017/0018554 A119 Jan 2017

Granted

9 Jan 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
G11C 5/14
Details of stores covered by group G11C11/00: power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or…
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type

Family

PCT/JP2011/067478Parent of this division · filed 29 Jul 2011

Application14/990,262Parent of this continuation · filed 7 Jan 2016

US 9,245,614 B2Parent of this division · filed 26 Jan 2016

US 2017/0018554 A1Pre-grant publication · published 19 Jan 2017

US 9,478,554 B2Parent of this continuation

Application14/234,479Parent of this division

Application14/990,262Parent of this division

US 2014/0177312 A1Published application

US 2016/0118389 A1Published application

US 9,865,604 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device and method of manufacturing semiconductor device

Life of this patent

Semiconductor device and method of manufacturing semiconductor device

Life of this patent

Abstract

Claims10