Semiconductor devices having bit lines and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorYongbum Kwon
Life of this patent
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Abstract
Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an active region of a substrate, isolation patterns provided on the substrate to face each other in a direction parallel to the bit line, a storage node contact provided between the isolation patterns to be in contact with a source/drain region provided in an upper portion of the active region, and a spacer provided between the bit line and the storage node contact. Here, the isolation patterns may include a material having an etch selectivity with respect to the spacer.
Claims20
A semiconductor device comprising:
- a substrate including an active region, an upper portion of the active region comprising a source/drain region:
- a bit line on the active region, the bit line crossing the active region and extending longitudinally in a first direction;
- a plurality of isolation patterns on a side of the bit line, the plurality of isolation patterns being arranged along the first direction and comprising a first isolation pattern and a second isolation pattern that is adjacent the first isolation pattern;
- a storage node contact between the first isolation pattern and the second isolation pattern, the storage node contact contacting the source/drain region;
- and
- a spacer comprising a first spacer and a second spacer secuentially stacked on the side of the bit line and extending between the bit line and the storage node contact and between the bit line and the plurality of isolation patterns,
- wherein a first portion of the second spacer that is between the bit line and the storage node contact comprises an uppermost end at a first height from the substrate, a second portion of the second spacer that is between the bit line and the first isolation pattern comprises an uppermost end at a second height from the substrate, and the second height is greater than the first height, and
- wherein a first portion of the first spacer that is between the bit line and the storage node contact comprises an uppermost end at a third height from the substrate, and the third height is greater than the first height.
A semiconductor device comprising:
- a substrate including an active region, an upper portion of the active region comprising a source/drain region;
- a bit line on the active region, the bit line crossing the active region and extending longitudinally in a first direction;
- a plurality of isolation patterns on a side of the bit line, the plurality of isolation patterns being arranged along the first direction and comprising a first isolation pattern and a second isolation pattern that is adjacent the first isolation pattern;
- a storage node contact between the first isolation pattern and the second isolation pattern, the storage node contact contacting the source/drain region;
- and
- a spacer between the bit line and the storage node contact, the spacer comprising a first spacer and a second spacer sequentially stacked on the side of the bit line,
- wherein both the second spacer and the storage node contact expose an upper portion of the first spacer, and
- wherein the second spacer includes a material different from both the first spacer and the plurality of isolation patterns.
Dependencies are inferred from the claim text.