Semiconductor integrated circuit

#In a development stage of an integrated circuit, an application program of a control circuit, such as a central processing unit (CPU) or a microprocessor, is written to a read-only memory (ROM). Subsequently, in a production stage, the control circuit is made with this program stored in the ROM. The ROM may be made by photolithographic masking so that data recorded are defined by a particular photolithographic mask configuration. Moreover, each memory cell is constituted by a transistor. Binary data memorized in this cell are defined by the fact that the transistor has been masked or not masked during an operation of implantation for enhancement or depletion. Then, the integrated circuit is tested. If the application of the integrated circuit is a rather complex one, errors are liable to occur in the program. To correct the errors, it may be necessary to make an integrated circuit again, which includes the control circuit and a new corrected program. This implies using a new set of masks, resulting in a relatively costly and lengthy operation.

#In order to provide flexibility in designing an integrated circuit, a random access memory (RAM) is used to store the application program of a control circuit. Errors of the application program may be corrected in the RAM and then the corrected program may be sent to the ROM to finalize the integrated circuit. Using an extra RAM may save time and cost as compared to changing ROM configuration. However, the extra RAM may inevitably occupy certain space or area, which may increase the size of the integrated circuit. Moreover, extra peripheral circuits are needed to control or support the extra RAM, which complicates circuit design and power management.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIG. 1A is a block diagram illustrating an integrated circuit in accordance with some embodiments.

#FIG. 1B is a schematic diagram illustrating an array of memory cells of a memory device as shown in FIG. 1A.

#The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

#Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

#FIG. 1A is a block diagram illustrating an integrated circuit in accordance with some embodiments.