Ultra low power wideband non-coherent binary phase shift keying demodulator using first order sideband filters with phase zero alignment

An ultra low power wideband non-coherent binary phase shift keying (BPSK) demodulation method using first order sideband filters with phase zero alignment, the ultra low power wideband non-coherent BPSK demodulation method comprises:

• a sideband separation and upper sideband signal delay step to output a lower sideband analog signal and a phase delayed analog signal to be delayed with preset phase from upper sideband analog signal, when a modulation signal in the input of the stage is divided to an upper sideband and a lower sideband by 1st order filters whose cutoff frequency is same as carrier frequency;
• a data demodulation step to demodulate digital data through a hysteresis circuit that latches an analog pulse signal to appear in the phase changing edge of BPSK modulation signal, in accordance with a phase difference between the lower sideband analog signal and the phase delayed analog signal being set to phase 0°;
• and
• a data clock recovery step to recover data clock using a digitized signal from the lower sideband analog signal and above demodulated digital data,
• wherein the sideband separation and upper sideband signal delay step comprises:
• a step to isolate lower sideband from the modulation signal by a 1st order low-pass filter (1st order LPF) whose cutoff frequency is the same as carrier frequency;
• a step to isolate upper sideband from the modulation signal by 1st order high-pass filter (1st order HPF) whose cutoff frequency is the same as carrier frequency;
• and
• a delay step to delay with preset phase from upper sideband analog signal that is the output of the 1st order HPF,
• the data demodulation step comprises:
• a step to generate an analog pulse signal to appear in the phase changing edge of the modulation signal by a subtracter, and the edge is caused by the difference of analog signals which are the lower sideband analog signal and the delayed upper sideband analog signal because the phase difference between the analog signals is set to phase 0°;
• and
• a step to demodulate digital data through latching the analog pulse signal by a Schmitt trigger that is a hysteresis circuit,
• wherein the data clock recovery step comprises:
• a step to convert a digital signal from the lower sideband analog signal by a comparator;
• and
• a step to recover a data clock for comparing the converted lower sideband analog signal with the demodulated digital data by an exclusive-NOR gate, and
• wherein the upper sideband analog signal that is from the output of 1st order filter, occurs faster than the lower sideband analog signal by π/2 or ¼ period of carrier frequency, and the phase delayed analog signal occurs through the delay circuit to delay π/2 or ¼ period of carrier frequency for finding phase changing edge with aligning phase 0° difference between the phase delayed analog signal and the lower sideband analog signal.