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US 9,858,976 B2Granted
Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel
AssigneeKabushiki Kaisha Toshiba
InventorsKazutaka Ikegami, Hiroki Noguchi
Life of this patent
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Abstract
According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.
Claims19
A nonvolatile RAM comprising:
- a memory cell array;
- a first circuit being allowed to access the memory cell array in a write operation using a first pulse;
- a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit;
- and
- a write circuit selectively outputting one of a third pulse and a fourth pulse as the first pulse on the basis of a select signal,
- wherein a width of the first pulse is longer than a width of the second pulse.
3 more elements
Dependencies are inferred from the claim text.