US 9,854,192 B2Granted

Digital unit cell with analog counter element

AssigneeRaytheon Company

InventorChristian M. Boemler

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Abstract

According to one aspect, embodiments herein provide a digital unit cell comprising a photodiode, an integration capacitor, a comparator configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time the voltage across the integration capacitor is greater than the threshold voltage, a charge subtraction circuit configured to receive the control signal at the first level and to discharge accumulated charge on the integration capacitor each time the control signal at the first level is received, at least one analog counter configured to receive the control signal at the first level from the comparator and to decrease a count voltage by a fixed amount each time the control signal at the first level is received from the comparator, and a counter readout circuit configured to provide the count voltage to an image processing circuit.

Claims20

Dependent claims

A digital unit cell comprising:

a photodiode;
an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over an integration period;
a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the threshold voltage;
a charge subtraction circuit coupled to the integration capacitor and to the comparator and configured to receive the control signal at the first level from the comparator and to discharge the accumulated charge on the integration capacitor each time the control signal at the first level is received from the comparator;
at least one analog counter coupled to the comparator and configured to receive the control signal at the first level from the comparator and to decrease a count voltage by a fixed amount each time the control signal at the first level is received from the comparator;
and
a counter readout circuit coupled to the at least one analog counter and configured to provide the count voltage to an image processing circuit at an end of the integration period.

4 more elements

Dependencies are inferred from the claim text.