Solid state imaging device, method of controlling solid state imaging device, and program for controlling solid state imaging device

An imaging device comprising:

• a pixel array having a first pixel unit configured to generate a first analog signal, a second pixel unit configured to generate a second analog signal and a third pixel unit configured to generate a third analog signal;
• wherein each of the first pixel unit, the second pixel unit and the third pixel unit includes a plurality of photodiodes configured to receive light through (i) a first color filter configured to transmit red light, (ii) a second color filter configured to transmit blue light, (iii) a third color filter configured to transmit green light or (iv) a fourth color filter configured to transmit red, blue and green light;
• wherein at least one of the plurality of photodiodes in the first pixel unit is configured to receive light through the fourth color filter;
• wherein the plurality of photodiodes in the first pixel unit share at least one of a floating diffusion, an amplification transistor and a selection transistor;
• a reference signal generator configured to generate a reference signal;
• a first comparator coupled to the first pixel unit via a first signal line extended in a first direction, wherein the first comparator is configured to compare the reference signal with the first analog signal;
• a second comparator coupled to the second pixel unit via a second signal line extended in the first direction, wherein the second comparator is configured to compare the reference signal with the second analog signal;
• a third comparator coupled to the third pixel unit via a third signal line extended in the first direction, wherein the third comparator is configured to compare the reference signal with the third analog signal, wherein the second comparator is arranged between the first comparator and the third comparator in a second direction perpendicular to the first direction;
• a first counter coupled to the first comparator;
• a second counter coupled to the second comparator;
• a third counter coupled to the third comparator, wherein the second counter is arranged between the first counter and the third counter in the second direction;
• and
• a switching circuitry configured to supply an output signal of the first comparator to an input terminal of the third counter.